The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 20, 2016
Filed:
Apr. 22, 2013
Jasper Design Automation, Inc., Mountain View, CA (US);
Victor Markus Purri, Sunnyvale, CA (US);
Caio Araújo Teixeira Campos, Belo Horizonte/Minas Gerais, BR;
Magnus Björk, Göteborg, SE;
Lawrence Loh, Milpitas, CA (US);
Claudionor Jose Nunes Coelho, Nova Lima/Minas Gerais, BR;
Jasper Design Automation, Inc., Mountain View, CA (US);
Abstract
A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.