South Pasadena, CA, United States of America

Lap Wai Chow

This inventor holds 23 USPTO granted patents and 2 published patent applications and 1 EPO patent, primarily in Integrated Circuit Security. Top assignees: Rambus Inc., Syphermedia International, Inc., Hughes Electronics Corporation. Active years: 1998-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lap Wai Chow. Retrieved from https://idiyas.com/inventor/lap-wai-chow-1bwkpbme

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 23 

% Patents Active = 47.8

 

Average Co-Inventor Count = 3.7

ph-index = 6

Forward Citations = 216(Granted Patents)


Location History:

  • South Pasaena, CA (US) (2001)
  • S. Pasadena, CA (US) (2012 - 2022)
  • South Pasadena, CA (US) (1998 - 2023)

Company Filing History:


Years Active: 1998-2023

Loading Chart...
Loading Chart...
Areas of Expertise:
FinFET Technology
Camouflage Techniques
Integrated Circuits
Secure Logic Locking
Physically Unclonable Functions
Programmable Micro Netlists
Reverse Engineering Protection
Ambiguous Features
Battery Charging Methods
Digital Circuits
23 patents (USPTO):Explore Patents

Title: Lap Wai Chow: Innovator in Integrated Circuit Protection

Introduction

Lap Wai Chow, an accomplished inventor based in South Pasadena, California, holds an impressive portfolio of 23 patents. His innovative work primarily focuses on technologies designed to enhance the security of integrated circuits, specifically against reverse engineering.

Latest Patents

Among his notable creations are two groundbreaking patents. The first is titled "Always-on FinFET with camouflaged punch stop implants for protecting integrated circuits from reverse engineering." This invention introduces a camouflaged application-specific integrated circuit (ASIC) that integrates a FinFET structure featuring a substrate of a first conductivity type. It presents a sophisticated design where a punch through stop (PTS) region electrically short circuits the source and drain regions, enhancing security against unauthorized access.

Another product of his ingenuity is the patent on "Electrically isolated gate contact in FINFET technology for camouflaging integrated circuits from reverse engineering." This patent outlines a method for adding source and drain contacts, along with a gate contact that remains electrically isolated. The process facilitates better protection of the fin structure, making it increasingly resistant to potential reverse engineering tactics.

Career Highlights

Throughout his career, Chow has made significant contributions while working at renowned companies such as Rambus Inc. and Syphermedia International, Inc. His technical expertise and innovative mindset have positioned him as a leading figure in the field of integrated circuit technology.

Collaborations

Chow has also collaborated with esteemed colleagues like James Peter Baukus and Ronald Paul Cocchi, which has allowed him to enrich his knowledge and skills while contributing to groundbreaking projects in the realm of integrated circuits.

Conclusion

With a strong portfolio of patents and a commitment to advancing technology, Lap Wai Chow stands out as a key innovator in the protection of integrated circuits. His work not only showcases his inventiveness but also reflects the importance of security in modern electronics. As technology continues to evolve, Chow's contributions will undoubtedly play a critical role in shaping the future of integrated circuit design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…