The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 2021

Filed:

Mar. 08, 2019
Applicant:

Inside Secure, Meyreuil, FR;

Inventors:

Lap Wai Chow, S. Pasadena, CA (US);

Bryan J. Wang, South Lake Tahoe, CA (US);

James P. Baukus, Westlake Village, CA (US);

Ronald P. Cocchi, Seal Beach, CA (US);

Assignee:

RAMBUS INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/785 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 27/0886 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/665 (2013.01); H01L 29/66795 (2013.01);
Abstract

A camouflaged FinFET is disclosed. The camouflaged FinFET comprises a fin and a gate, disposed over and perpendicular to the fin. The fin includes a source region of a first conductivity type, a drain region of the first conductivity type, a channel region of a second conductivity type, the channel region disposed between the source region and the drain region, and a camouflaged fin region of the second conductivity type, the camouflaged Fin region at least partially rendering the camouflaged FinFET in an always-on condition and having a planar layout substantially indistinguishable from a fin region of an uncamouflaged FinFET.


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