Kuo-Reay Peng

This inventor holds 23 USPTO granted patents, primarily in CMOS Technology. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 1998-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kuo-Reay Peng. Retrieved from https://idiyas.com/inventor/kuo-reay-peng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 23

% Patents Active = 95.7

Average Co-Inventor Count = 4.0

ph-index = 12

Forward Citations = 448(Granted Patents)

Location History:

FounSan, TW (1998)
Kaoushing, TW (1999)
Fung-San, TW (1999)
Kaoushuy, TW (1999)
Kuoshung, TW (1999)
Faung-San, TW (1998 - 2000)
Faung-Shan, TW (2000)
TarnySan, TW (2000)
Fangshan, TW (2001)
Tansung, TW (2002)
Funsung, TW (2001 - 2003)
Tainan, TW (2002 - 2003)
Hsin-chu, TW (1999 - 2005)
Feng-Shan, TW (2005)

Company Filing History:

23 out of 42,810

Taiwan Semiconductor Manufacturing Comp. Ltd.

patents

Years Active: 1998-2005

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Areas of Expertise:

CMOS Circuits

MIM Capacitors

ESD Protection

Flash EEPROM

Damascene Inductor

Copper Process

High Breakdown Voltage

Erase Method

Capacitance Reduction

Radio Frequency Capacitors

Sub-0.18 um Process

23 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6881996 - Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer (2005-04-19),

2. 6876041 - ESD protection component (2005-04-05),

3. 6812088 - Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer (2004-11-02),

4. 6667217 - Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process (2003-12-23),

5. 6661060 - Low capacitance ESD protection device (2003-12-09),

6. 6614693 - Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROM (2003-09-02),

7. 6610262 - Depletion mode SCR for low capacitance ESD input protection (2003-08-26),

8. 6472721 - Dual damascene interconnect structures that include radio frequency capacitors and inductors (2002-10-29),

9. 6448123 - Low capacitance ESD protection device (2002-09-10),

10. 6329234 - Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow (2001-12-11),

11. 6303454 - Process for a snap-back flash EEPROM cell (2001-10-16),

12. 6122201 - Clipped sine wave channel erase method to reduce oxide trapping charge (2000-09-19),

13. 6055183 - Erase method of flash EEPROM by using snapback characteristic (2000-04-25),

14. 6049486 - Triple mode erase scheme for improving flash EEPROM cell threshold (2000-04-11),

15. 6049484 - Erase method to improve flash EEPROM endurance by combining high voltage (2000-04-11),

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Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]