Taiwan Semiconductor Manufacturing Comp. Ltd.

Kuo-Reay Peng

Jian-Hsing Lee

Ming-Chou Ho

Kong-Beng Thei

Ta-Hsun Yeh

Chun-Hon Chen

Yen-Shih Ho

Ssu-Pin Ma

Heng-Ming Hsu

Juang-Ke Yeh

Juang-Ker Yeh

Chi-Wu Chou

Shui-Hung Chen

Jiaw-Ren Shih

Jung-Ke Yeh

Shih-Chyi Wong

Hsiu-Han Liao

Chia-Ta Hsieh

Di-Son Kuo

Hung-Cheng Sung

Yai-Fen Lin

Jau-Yuann Chung

Jaung-Ke Yeh

A metal-insulator-metal (MIM) capacitor structure and method of fabrication for CMOS circuits having copper interconnections are described. The method provides metal capacitors with high figure of merit Q (X/R) and which does not require additional masks and metal layers. The method forms a copper capacitor bottom metal (CBM) electrode while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (SiN) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer is used to protect the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

Metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer

The present invention provides an ESD protection component, comprising at least two MOS field effect transistors (FETs) of a first conductivity type and a first well having a first conductivity type. The two MOS FETs have two parallel gates formed on a first semiconductive layer having a second conductivity type. The first well formed on the first semiconductive layer is comprised of a connecting area formed between the MOS FETs, two parallel extension areas formed perpendicular to the gates of the MOS FETs, and a first doping area of the second conductivity type formed in the connecting area. Two SCR are formed with drains of the MOS FETs, the first semiconductive layer, the first well and the first doping region. With the combination of the SCR and NMOS FET, ESD protection efficiency can be substantially enhanced.

ESD protection component

This MIM structure provides metal capacitors with high figure of merit Q (X /R) and does not require additional masks and metal layers. A copper capacitor bottom metal (CBM) electrode is formed, while concurrently forming the pad contacts and level of copper interconnections by the damascene process. An insulating (Si N ) metal protect layer is formed on the copper and a capacitor interelectrode dielectric layer is formed. A metal protecting buffer protects the thin interelectrode layer, and openings are etched to pad contacts and interconnecting lines. A TiN/AlCu/TiN metal layer is deposited and patterned to form the capacitor top metal (CTM) electrodes, the next level of interconnections, and to provide a pad protect layer on the copper pad contacts. The thick TiN/AlCu/TiN CTM electrode reduces the capacitor series resistance and improves the capacitor figure of merit Q, while the pad protect layer protects the copper from corrosion.

Method for making a new metal-insulator-metal (MIM) capacitor structure in copper-CMOS circuits using a pad protect layer

A process for integrating the fabrication of a thick, copper inductor structure, with the fabrication of narrow channel length CMOS devices, has been developed. The integrated process features the use of only one additional photolithographic masking step, used to form the opening in an IMD layer, that will accommodate the subsequent inductor structure. After forming damascene type openings in the same IMD layer, in the CMOS region, copper is deposited and then defined, to result in a thick, copper inductor structure, in the opening in the IMD layer, in a first region of a semiconductor substrate, as well as to result in copper interconnect structures, in the damascene type openings located in a second region of the semiconductor structure, used for the narrow channel length CMOS devices. The use of a thick, copper inductor structure, equal to the thickness of the IMD layer, results in increased inductance, or an increased quality factor, when compared to counterparts formed with thinner metal inductors.

Method of fabricating a damascene copper inductor structure using a sub-0.18 um CMOS process

An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P&plus; diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N&plus; diffusion) next to the it. The drain and the P&plus; diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P&plus; diffusion) is located on either side of each source (N&plus; diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P&plus; diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.

Low capacitance ESD protection device

A combination erase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. A first embodiment method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate, followed by a source erasing to further remove charges from the floating gate, and finally followed by a channel erasing to detrap charges. A second embodiment begins with a negative gate erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a source erasing to detrap the tunneling oxide of the EEPROM cell. A third embodiment begins with a source erasing having a incremental stepping of the voltages to remove the charges from the floating gate. This followed by a channel erasing to detrap the tunneling oxide of the EEPROM cell.

Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROM

The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of a heavily doped P&plus; contact area residing in an N well region on a P substrate and electrically connected to the input pad of active integrated field effect transistor devices. NFET devices with floating gates and drains to reduce capacitance are located in the substrate near the N-well. The NFET source elements as well as the substrate are connected to ground. The NFETs are isolated from the N-well and associate P&plus; contact area by shallow trench isolation (STI) structures that reduce the NFET drain to substrate and N-well to substrate junction boundary area with a subsequent reduction in the junction capacitance. A voltage pulse from an ESD event will cause the SCR structure and associated parasitic bipolar transistors to trigger providing a path to ground for the ESD current, thereby protecting the internal circuits from damage.

Depletion mode SCR for low capacitance ESD input protection

In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.

Dual damascene interconnect structures that include radio frequency capacitors and inductors

An ESD protection device for the protection of MOS circuits from high ESD voltages by arranging an N-well of very short length in a P-well or P-substrate. Diffused into this N-well is a P&plus; diffusion. Together they form a diode and part of a parasitic pnp bipolar transistor which is shared by two parasitic SCRs. The junction capacitance of this N-well is very low and in the order of 0.03 pF. Disposed to either side of this N-well is an NMOS transistor which has its drain (an N&plus; diffusion) next to the it. The drain and the P&plus; diffusion are coupled together and connect to a chip pad, which receives the ESD. The chip pad couples to the MOS circuits to be protected. The junction capacitance of both drains combined is in the order of 0.24 pF, so that the junction capacitance of the N-well is about one tenth of that of both drains. A P&plus; diffusion is located on either side of each source (N&plus; diffusion) and together are coupled to a reference potential. An ESD pulse applied to the chip pad exceeds the electric field strength of the channel of the NMOS transistors and drives them into conduction and snapback mode. Hole and electron currents between components of the NMOS transistors and the N-well and its P&plus; diffusion next turn on both SCRs and conduct the ESD current safely from the chip pad to the source and ground.

Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow

The present invention provides method to fabricate a snap-back flash EEPROMS device. The method begins by forming a gate structure 22 24 28 26 on a substrate. The gate structure comprises: a tunnel oxide layer 22, a floating gate 24, integrate dielectric layer 28, and a control gate 26. A drain 14 is formed adjacent to the gate structure by an masking 51 and ion implant process. Next, a source side doped region 18 is formed adjacent to and under a portion of the gate structure 22 24 28 26 by an masking and ion implant process. Spacers 32 are now formed on the sidewalls of the gate structure. A source 20 is formed overlapping portion of the side source doped region 18 and adjacent to the spacers 32. The side source doped region has a lower dopant concentration than the source 20. This method forms a snap-back memory cell wherein the side source doped region 18 is used to apply a high voltage to operate the EEPROM cell in a snap-back erase mode.

Process for a snap-back flash EEPROM cell

A method to channel erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to channel erase a flash EEPROM cell begins by removing the charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a relatively large clipped sinusoidal negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a moderately large positive voltage pulse to a first diffusion region. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain, the source and a second diffusion well are allowed to float.

Clipped sine wave channel erase method to reduce oxide trapping charge

A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles, while preventing damage due to high field stress in the tunneling oxide. The method to erase a flash EEPROM cell begins by applying a relatively high positive voltage pulse to the source of the EEPROM cell. Simultaneously a ground reference voltage is applied to the drain and to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate. This will cause a parasitic bipolar transistor to conduct and go into a snap back condition reducing the voltage field in the tunneling oxide.

Erase method of flash EEPROM by using snapback characteristic

A method to erase data from a flash EEPROM is disclosed. Electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by erasing the flash EEPROM cell by first applying a high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a ground reference potential is applied to the semiconductor substrate and the control gate. At this same time the drain is floating. Floating the source and drain and applying the ground reference potential to the semiconductor substrate then detraps the flash EEPROM cell. At the same time, a relatively large negative voltage pulse is applied to the control gate.

Erase method to improve flash EEPROM endurance by combining high voltage

A multiple phase method to erase data from a flash EEPROM eliminates electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by negative gate erasing to remove charges from the floating gate by first applying a first relatively large negative voltage pulse to the control gate. Concurrently a first moderately large positive voltage pulse is applied to the source. Also, concurrently a ground reference potential is applied to the first well and the semiconductor substrate, and the drain and second well are disconnected to allow the drain and second well to float. The flash EEPROM cell is then source erased to further remove charges from the floating gate by floating the drain and the second well and concurrently applying the ground reference potential to the semiconductor substrate, the drain, and the first well. Simultaneously, a relatively large positive voltage pulse is applied to the source. The flash EEPROM is then channel erased to detrap charges from the tunneling oxide by applying a second relatively large negative voltage pulse to the control gate of the EEPROM cell and concurrently applying a second moderately large positive voltage pulse to the first well. At this same time, a ground reference potential is applied to the semiconductor substrate and the drain, the source, and the second well are floated.

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Tainan, Taiwan

Kuo-Reay Peng