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For the Inventor, By the Inventor

Tainan, Taiwan

Kun-Ching Chen

USPTO Granted Patents = 19

Average Co-Inventor Count = 3.1

ph-index = 9

Forward Citations = 452(Granted Patents)


Company Filing History:

goldMedal19 out of 1,867 
 
Advanced Semiconductor Engineering, Inc.
 patents

Years Active: 1999-2014

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19 patents (USPTO):
1. 8720053 - Process of fabricating a circuit board (2014-05-13),
2. 7125745 - Multi-chip package substrate for flip-chip and wire bonding (2006-10-24),
3. 7061347 - High frequency substrate comprised of dielectric layers of different dielectric coefficients (2006-06-13),
4. 7061084 - Lead-bond type chip package and manufacturing method thereof (2006-06-13),
5. 6750397 - Thermally enhanced semiconductor build-up package (2004-06-15),
6. 6737300 - Chip scale package and manufacturing method (2004-05-18),
7. 6714421 - Flip chip package substrate (2004-03-30),
8. 6701614 - Method for making a build-up package of a semiconductor (2004-03-09),
9. 6680529 - Semiconductor build-up package (2004-01-20),
10. 6642612 - Lead-bond type chip package and manufacturing method thereof (2003-11-04),
11. 6534852 - Ball grid array semiconductor package with improved strength and electric performance and method for making the same (2003-03-18),
12. 6528882 - Thermal enhanced ball grid array package (2003-03-04),
13. 6455941 - Chip scale package (2002-09-24),
14. 6423622 - Lead-bond type chip package and manufacturing method thereof (2002-07-23),
15. 6313413 - Wire structure of substrate for layout detection (2001-11-06),

Title: Innovations of Kun-Ching Chen in Circuit Board Fabrication

Introduction: Kun-Ching Chen, based in Tainan, Taiwan, is a prolific inventor with a remarkable portfolio of 19 patents. His contributions primarily focus on advanced semiconductor technologies, particularly in the fabrication of circuit boards and multi-chip package substrates.

Latest Patents: Among his latest innovations, Chen has developed a patented process for fabricating a circuit board. This process involves layering a dielectric layer, a circuit layer with distinct pad and trace regions, and an insulation layer that effectively covers the trace region while maintaining a reduced thickness in the pad region.

Another notable patent is the design of a multi-chip package substrate that accommodates both flip-chip bumping and wire-bonding applications. This substrate is engineered with a top and bottom surface, featuring bumping and wire-bonding pads on the top. To enhance reliability, a pre-solder material fully covers the bumping pads, preventing oxidation during packaging and mitigating the risk of Au intermetallics during chip bumps.

Career Highlights: Kun-Ching Chen plays a significant role at Advanced Semiconductor Engineering, Inc., a leader in the semiconductor manufacturing sector. His expertise in circuit design and fabrication processes has positioned him as a key contributor to the company’s technological advancements.

Collaborations: Throughout his career, Chen has collaborated with esteemed colleagues such as Yi-Chuan Ding and Yung-I Yeh, contributing to a synergy that fosters innovation and excellence in semiconductor technologies.

Conclusion: Kun-Ching Chen’s extensive patent portfolio and his work at Advanced Semiconductor Engineering, Inc. showcase his significant impact in the field of semiconductor technology. His innovative processes and collaborative efforts with fellow experts continue to enhance the reliability and functionality of modern electronic devices.

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