Advanced Semiconductor Engineering, Inc.

Kun-Ching Chen

Yi-Chuan Ding

Su Tao

Yung-I Yeh

Yung I Yeh

In-De Ou

Chun-Chi Lee

Chun-Che Lee

Shyh-Ing Wu

Wu-Chang Wang

Xin Hui Lee

Ho-Ming Tong

Shih-Chang Lee

Chih-Ming Chung

Chun Hung Lin

Po-Jen Cheng

Chang-Chi Lee

Sung-Mao Wu

Yun-Hsiang Tien

Tao-Yu Chen

Ming-Loung Lu

Han-Hsiang Huang

I Zeng Lee

Yire-Zine Lee

Yei-Shen Wu

Chun-Hsiung Huang

A process for fabricating a circuit board that includes a dielectric layer, a circuit layer, and an insulation layer. The circuit layer is disposed on the dielectric layer and has a pad region and a trace region. The insulation layer is disposed on the circuit layer and covers the trace region. Here, a thickness of the pad region is less than a thickness of the trace region.

Process of fabricating a circuit board

A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Multi-chip package substrate for flip-chip and wire bonding

A high frequency substrate includes a first metal layer, a first dielectric layer, a second metal layer, a second dielectric layer and a high-frequency signal transmission line. The first dielectric layer is formed on the first metal layer, and the second metal layer is formed on the first dielectric layer. The first and second metal layers are maintained in a stable voltage status due to the high dielectric coefficient of the first dielectric layer. Besides, the second dielectric layer is formed on the second metal layer. High speed and high frequency transmission are achieved when signals transmitting in the high-frequency transmission line formed on the second dielectric layer due to the low dielectric coefficient of the second dielectric layer.

High frequency substrate comprised of dielectric layers of different dielectric coefficients

A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections. This invention also provides a method of producing a multilayer substrate for use in forming a lead-bond type chip package

Lead-bond type chip package and manufacturing method thereof

A semiconductor build-up package includes a die, a metal carrier, and a plurality of dielectric layers. The metal carrier has a surface with a cavity for supporting the die. The surface of metal carrier is coplanar to the active surface of die for building up a plurality of dielectric layers. Each dielectric layer has metal columns for inner electrical connection. The metal carrier covers passive surface and sides of the die with a larger area for heat dissipating, so the heat generated from the die is dissipated fast through the metal carrier.

Thermally enhanced semiconductor build-up package

A chip scale package mainly comprises a substrate attached to the active surface of a semiconductor chip through an anisotropic conductive adhesive film (ACF). The substrate is provided with a plurality of contact pads on the lower surface thereof and a plurality of solder pads on the upper surface thereof wherein the contact pads are electrically coupled to corresponding solder pads. A plurality of metal bumps provided on the contact pads of the substrate. The metal bumps on the substrate are electrically coupled to corresponding bonding pads on the chip through the ACF. The side portions of the substrate and the ACF are sealed in a package body. The present invention further provides a method of making the chip scale package at the wafer level. The method is characterized by attaching substrates onto the chips of a wafer one by one so as to greatly reduce the problems associated with CTE mismatch between the wafer and the substrate thereby significantly enhancing the product yield.

Chip scale package and manufacturing method

A flip chip package substrate is disclosed. The substrate is correspondingly flip chip bonded to a first chip, a second chip, and so on, wherein these chips are of similar type of pad arrangement but of different pad pitches. The top face of the flip chip package substrate is provided with a plurality of bump pad groups, and these bump pad groups are respectively provided with a plurality of bump pads in the sequence of a first bump pad, a second bump pad, and so on, and a plurality of bump pads of the same bump pad group are electrically connected with each other, and the positions of the first bump pads are respectively corresponding to the positions of the second pads, and the rest may be inferred by analogy. Hence, these chips share the same flip chip package substrate.

Flip chip package substrate

A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Method for making a build-up package of a semiconductor

A semiconductor build-up package includes a die, a circuit board and at least a dielectric layer. The circuit board has a surface for building up the dielectric layer, and the surface has a cavity for accommodating the die. The inside of multi-layer circuit board has conductive traces for expanding the electrical function of semiconductor build-up package. Each dielectric layer has conductive columns so that the die may electrically connect with the outermost dielectric layer. At least a conductive column is bonded on the surface of the multi-layer circuit board for inner electrical connection.

Semiconductor build-up package

A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections. This invention also provides a method of producing a multilayer substrate for use in forming a lead-bond type chip package.

Disclosed are metal reinforced layers disposed at the upper and lower surfaces of the thin substrate to reinforce the strength of the thin substrate. With reinforced strength, the thin substrate is not susceptible to deform due to temperature fluctuation during packaging process, and thus the warpage for the semiconductor package is significantly eliminated. According to another aspect of the present invention, the metal reinforced layer at the lower surface of the thin substrate is functioned as a ground plane for the ball grid array (BGA) semiconductor package for better grounding effect. The present invention provides an optimal design for the return current path and impedance matching control. Besides, in high frequency application, the metal reinforced layer also can reduce the noise and cross talk among the signal lines of the ball grid array (BGA) semiconductor package.

Ball grid array semiconductor package with improved strength and electric performance and method for making the same

A thermal enhanced ball grid array package is provided. The substrate for the package includes a metal core layer and at least a first patterned wiring layer provided thereon. A first insulating layer is provided between the first patterned wiring layer and the metal core layer. At least a second patterned wiring layer is provided on the substrate, opposite to the surface having the first patterned wiring layer. A second insulating layer having solder balls between the second patterned wiring layer and the metal core layer. The second patterned wiring layer is electrically connected to the first patterned wiring layer. Blind vias are provided in the second patterned wiring layer and the second insulating layer. A heat conductive material or solder material is filled into the blind vias to form thermal balls. The heat from the chip to the metal core layer is transferred directly through the thermal balls.

Thermal enhanced ball grid array package

A chip scale package comprises a film substrate attached to the active surface of a semiconductor chip by an adhesive layer. The adhesive layer has a plurality of apertures formed corresponding to bonding pads on the chip. The film substrate includes a film and a plurality of conductive leads formed thereon. The film has a plurality of first openings formed corresponding to the apertures of the adhesive layer and a plurality of second openings. Each lead on the film has a first end portion projecting into one of the first openings of the film and a second end portion exposed from one of the second openings of the film. Each aperture and corresponding first opening are filled with a conductive paste embedding the first end portion of one lead therein so as to electrically connect the bonding pads of the chip and the conductive leads of the film substrate. A plurality of solder bumps formed on the second end portions of leads through the second openings of the film. This invention further provides a method of making the chip scale package.

Chip scale package

The substrate of the present invention mainly includes a plurality of bonding pads, a plurality of ball pads, a plurality of traces, a plurality of holes, a first wire and a second wire. The bonding pads and ball pads are located on a first surface of the substrate and are connected to one another by the traces. The first wire is arranged at the edge of the first surface of the substrate, the second wire is arranged at a slot area of a second surface of the substrate which is adhesively covered by a solder mask and further has two ends connecting to the first wire. The holes connect the first surface to the second surface. The traces are connected the bonding pads and ball pads of the first surface by passing through the corresponding holes and a slot area to the second wire of the second surface to form closed loops. In the slot area, the solder mask adhesively covers the traces. During the slot sawing processes of the slot area, some parts of the traces in the slot area and the second wire are cut to form an opened loop. Then the ends of the traces at the edge of the slot area have little lateral malleability. Thus the adjacent ends of traces cannot be connected to one another; so the substrate of the present invention can use the socket of the test machine to increase efficiency.

Growing community of inventors

Tainan, Taiwan

Kun-Ching Chen