The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 24, 2006
Filed:
Apr. 28, 2004
Kun-ching Chen, Tainan, TW;
Yi-chuan Ding, Kaohsiung, TW;
Po-jen Cheng, Kaohsiung, TW;
Chih-ming Chung, Kaohsiung, TW;
Yun-hsiang Tien, Fengshan, TW;
Kun-Ching Chen, Tainan, TW;
Yi-Chuan Ding, Kaohsiung, TW;
Po-Jen Cheng, Kaohsiung, TW;
Chih-Ming Chung, Kaohsiung, TW;
Yun-Hsiang Tien, Fengshan, TW;
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
Abstract
A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.