Tokyo, Japan

Kimio Ueda

This inventor holds 37 USPTO granted patents, primarily in Semiconductor Circuits. Top assignees: Mitsubishi Denki Kabushiki Kaisha, Other. Active years: 1983-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kimio Ueda. Retrieved from https://idiyas.com/inventor/kimio-ueda

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 97.3

Average Co-Inventor Count = 2.1

ph-index = 11

Forward Citations = 731(Granted Patents)


Location History:

  • Itami, JP (1989 - 1995)
  • Hyogo, JP (1991 - 2002)
  • Tokyo, JP (1983 - 2006)

Company Filing History:


Years Active: 1983-2006

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Areas of Expertise:
Clock Recovery Circuit
Data Recovery Circuit
High Linearity Mixer
Multiplexer Circuit
Transistor Leakage
Silicon-on-Insulator
Electrostatic Protection
Current Mode Logic
Power Consumption Reduction
Integrated Circuit Device
BiCMOS Logic Circuit
Light-Actuated Superconducting
37 patents (USPTO):Explore Patents

Title: The Innovative Mind of Kimio Ueda

Introduction

Kimio Ueda, an esteemed inventor based in Tokyo, Japan, has made significant contributions to the field of semiconductor technology. With an impressive portfolio of 37 patents, Ueda stands out as a prominent figure in innovation, particularly in the realms of clock and data recovery circuits.

Latest Patents

Among his latest patents is a groundbreaking "Half-rate clock and data recovery circuit." This invention features a phase detector that operates at a half-rate, including a charge pump circuit, a low pass filter, and a voltage-controlled oscillator. The unique phase detector incorporates a selector circuit, which processes uninverted and inverted signals from respective latches and outputs retimed signals to maintain performance efficiency, producing a full-rate output from a half-rate input, ultimately enhancing the operating margin of the circuit.

Another notable patent is the "Semiconductor device having steady substrate potential." This invention covers a semiconductor device with a Silicon-On-Insulator (SOI) structure designed to stabilize substrate potential without increasing the device's surface area. In Ueda's design, the integrated circuit is fabricated within an internal circuit region, with wiring layers supplying stable potential located away from critical circuit areas, thus optimizing space and functionality.

Career Highlights

Ueda has made valuable contributions during his tenure at Mitsubishi Denki Kabushiki Kaisha, honing his skills and expertise in semiconductor innovations. His work has on numerous occasions showcased the fusion of theoretical knowledge and practical application, cementing his status as a skilled inventor.

Collaborations

Throughout his career, Kimio Ueda has collaborated with notable individuals such as Koichiro Mashiko and Yoshiki Wada. These partnerships have not only enriched his work but have also played a crucial role in pushing the boundaries of semiconductor technology.

Conclusion

Kimio Ueda’s innovative spirit and dedication to advancing technology are evident through his extensive patent portfolio and collaborative efforts. His work continues to influence the semiconductor industry, driving advancements that benefit various applications and ensuring a legacy of innovation for future generations.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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