Mitsubishi Denki Kabushiki Kaisha

Other

Kimio Ueda

Koichiro Mashiko

Yoshiki Wada

Hiroyuki Morinaka

Toru Nakura

Hiroshi Makino

Yasunobu Nakase

Hisayasu Satoh

Hiroaki Suzuki

Yuuichi Hirano

Hiroshi Komurasaki

Nagisa Sasaki

Masahiro Ueda

Hirotada Kuriyama

Toru Shiomi

Toshiaki Hanibuchi

Hisayasu Sato

Takanori Hirota

Hideki Andou

Jun Takasoh

A half-rate clock and data recovery circuit includes a phase detector capable of operating at a half-rate, a charge pump circuit, a low pass filter, and a voltage controlled oscillator. The phase detector includes a selector circuit which receives uninverted and inverted signals from respective latches of the phase detector and an uninverted and inverted half-rate clock and outputs uninverted and inverted retimed signals supplied to the charge pump so that the charge pump produces a full-rate output in response to a half-rate input. The circuit provides greater operating margin.

Half-rate clock and data recovery circuit

A semiconductor device having an SOI structure having a contact for making steady the potential of a semiconductor substrate without involvement of an increase in the surface of the semiconductor device. In a semiconductor chip, an integrated circuit is fabricated within an internal circuit region, and a plurality of buffer circuits are fabricated within buffer regions. Wiring layers for supplying steady potential are formed in the area of the semiconductor chip other than the internal circuit region and the buffer regions; for example, at four corners of the semiconductor chip, and contacts for connecting the wiring layers and the semiconductor substrate are formed in the area of the integrated circuit which is not assigned for fabrication of integrated circuits, thus eliminating a necessity for ensuring a location specifically allocated for formation of the contacts.

Semiconductor device having steady substrate potential

A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (V &minus;V )<(V &minus;V ) is established, where V is a bias voltage applied to the gate of the first MOS transistor, V is a bias voltage applied to the gate of the second MOS transistor, and V is a threshold voltage of the first MOS transistor, the bias voltages V and V being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.

High linearity, high gain mixer circuit

In a multiplexer, flip-flops for timing control are interposed between a control signal generating circuit and a four-to-one selector, and a flip-flop is interposed between a quarter divider and flip-flops provided for data input. A sum of delay times of the quarter divider and the control signal generating circuit and a setup time of the flip-flops for timing control is merely required to fall within one clock cycle, and therefore an operation speed can be high.

Fast operating multiplexer

A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both sides of the gate electrode in the gate length direction Y. An n type gate width determining layer is provided on the surface of the semiconductor substrate to sandwich the source/drain layers in the width direction X of the gate electrode, which determines a gate width of the gate electrode. The source/drain layers and the gate width determining layer are isolated by PN junction.

Semiconductor device with reduced transistor leakage current

A Silicon-On-Insulator (SOI) CMOS circuit includes a plurality of PMOS transistors connected in series to each other and at least one NMOS transistor connected to one of the PMOS transistors. The NMOS transistor has its body connected to a low reference potential having a value of ground. The SOI CMOS circuit further includes a body potential generating circuit which generates a body potential between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential. The body potential generating circuit applies the high potential to the bodies of the PMOS transistors.

Silicon-on-insulator CMOS circuit

First to third D flip-flops, fourth to sixth D flip-flops, and a delay circuit are provided. The first to third D flip-flops frequency-divide a clock signal. The fourth to sixth D flip-flops are provided corresponding to the first to third D flip-flops for latching frequency-divided outputs from corresponding D flip-flops and outputting them in synchronization with the clock signal. Accordingly, the frequency-divided outputs from the fourth to sixth D flip-flops are synchronized with the clock signal with a delay of prescribed time. The delay circuit outputs the clock signal after a delay of the prescribed time. Thus, the output of the delay circuit and the frequency-divided outputs are synchronized without delay.

Synchronous frequency dividing circuit

A field shield portion consisting of a kind of transistor is formed to electrically insulate an NMOS region of a memory cell from other regions. The field shield portion includes a field shield gate electrode layer, a p type region and a gate insulating film. Threshold value of this transistor is set higher than the power supply voltage, and field gate electrode layer thereof is in a floating state. It is unnecessary to provide a contact portion for applying a prescribed voltage at field shield gate electrode layer. Therefore, the region for forming the contact portion in field shield gate electrode layer can be reduced. As a result, a semiconductor device of which layout area is reduced, is provided.

SOI Semiconductor device with field shield electrode

A body voltage controlled semiconductor integrated circuit which can solve a problem of a conventional CMOS inverter in that it cannot operate at a supply voltage beyond the built-in voltage of the CMOS transistors if their body electrodes are each connected to their own gate electrodes rather than to their source electrodes to quicken the operation of the CMOS inverter. A voltage divider circuit is provided which conducts during the operation of the CMOS transistors of the inverter so that the body voltages of the PMOS transistor or the NMOS transistor of the inverter is varied in the direction of reducing their threshold voltages. By controlling the size of electrodes and the voltages applied to the body electrodes of transistors constituting the voltage divider circuit, it becomes possible to operate the CMOS inverter at the supply voltage beyond the built-in voltage.

Body voltage controlled semiconductor integrated circuit

According to a structure in which each transistor of an output buffer transistor group of a gate array structure is electrically isolated, each body potential is set independent Also, a diode-connected transistor is provided between power supplies. An element not used in the output buffer transistor group can be connected without short-circuiting power supply lines between independent power supply lines to form an electrostatic protection circuit that is efficient in layout.

Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing various types of surge

A Silicon-On-Insulator (SOI) CMOS circuit comprises a plurality of PMOS transistors connected in series to each other, each of the plurality of PMOS transistors having its body and gate connected to each other, and at least an NMOS transistor connected to one of the plurality of PMOS transistors, the NMOS transistor having its body connected to a low reference potential having a value of ground. The SOI CMOS circuit can further comprise a plurality of potential limiting circuits each connected between the body and gate of each of the plurality of PMOS transistors, for setting a lower limit of the potential of the body of each of the plurality of PMOS transistors to a voltage between a high reference potential and a potential obtained by subtracting a built-in potential from the high reference potential.

Silicon-on-insulator circuit having series connected PMOS transistors each having connected body and gate

An object is to obtain an amplification circuit which provides a high gain even with a low-voltage power supply. The amplification circuit comprises an MOS transistor (M1) having a gate receiving an amplified signal (RFin), a source electrically connected to ground, and a drain electrically connected to a supply voltage (VDD), wherein the back gate-source voltage (Vbs) of the MOS transistor (M1) is made larger as the gate-source voltage (Vgs) of the MOS transistor (M1) becomes larger, thereby making the threshold voltage (VT) of the MOS transistor (M1) smaller.

Amplification circuit

A current mode logic circuit has a first and second NMOS transistors N1 and N2, an input terminal IN connected to both gates of the first and second NMOS transistors N1 and N2 to input data, a reference voltage input terminal REF, an output terminal OUT connected to a drain of the first NMOS transistor N1, and a current power source I connected both sources of the first and second NMOS transistors N1 and N2. Body terminals of the first and second NMOS transistors N1 and N2 are connected to the input terminal IN and the reference terminal REF, respectively so that the body voltage of each of the first and second NMOS transistors N1 and N2 is controlled.

Current mode logic circuit, source follower circuit, and flip flop

Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc&gt;d2&gt;d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).

Counter circuit

MOS devices are formed on a wafer having a thick silicon layer 3a and a thin silicon layer 3b formed on a buried oxide film. The MOS device formed in the thick silicon layer 3a is activated in a partial depletion type mode. Further, the MOS device formed in the thick silicon layer 3b is activated in a perfect depletion type mode. Therefore, a low leakage current and a high-speed operation can be achieved simultaneously. It is thus possible to solve problems that an integrated circuit must be formed by either one of the partial depletion type device and the perfect depletion type device, and the low leakage current and the high-speed operation are hard to come to fruition simultaneously.

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Tokyo, Japan

Kimio Ueda