The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2003

Filed:

Jul. 12, 2002
Applicant:
Inventors:

Hiroshi Komurasaki, Tokyo, JP;

Hisayasu Sato, Tokyo, JP;

Kimio Ueda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06G 7/12 ; G06G 7/16 ; G06F 7/44 ;
U.S. Cl.
CPC ...
G06G 7/12 ; G06G 7/16 ; G06F 7/44 ;
Abstract

A mixer circuit includes a first signal input terminal connected to the gate of a first MOSFET, and a second signal input terminal connected to the gate of a second MOSFET. The mixer circuit is configured such that a relationship (V &minus;V )<(V &minus;V ) is established, where V is a bias voltage applied to the gate of the first MOS transistor, V is a bias voltage applied to the gate of the second MOS transistor, and V is a threshold voltage of the first MOS transistor, the bias voltages V and V being each defined with respect to the source bias voltage of the second MOS transistor. This can implement high linearity mixer circuit even when operated at a low power supply voltage.


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