Sapporo, Japan

Katsuhiro Tomioka

This inventor holds 7 USPTO granted patents and 1 published patent application and 5 EPO patents. Top assignees: Hokkaido University, Japan Science and Technology Agency, Sharp Kabushiki Kaisha Corporation. Active years: 2014-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Katsuhiro Tomioka. Retrieved from https://idiyas.com/inventor/katsuhiro-tomioka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 7 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.0

ph-index = 3

Forward Citations = 39(Granted Patents)


Location History:

  • Sapporo, JP (2014 - 2019)
  • Hokkaido, JP (2014 - 2024)

Company Filing History:


Years Active: 2014-2024

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7 patents (USPTO):Explore Patents

Title: Katsuhiro Tomioka: Innovator in Semiconductor Technology

Introduction

Katsuhiro Tomioka is a prominent inventor based in Sapporo, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 7 patents. His work focuses on innovative solutions that enhance the performance and efficiency of electronic devices.

Latest Patents

One of his latest patents is a complementary switch element. This invention includes a first tunneling field-effect transistor (TFET) with a first conductive channel and a second TFET with a second conductive channel. Each TFET features a group IV semiconductor substrate doped in a first conductive type, along with a nanowire made of a group III-V compound semiconductor. The design incorporates a first electrode connected to the group IV semiconductor substrate, a second electrode linked to the nanowire, and a gate electrode. The nanowire consists of a first area connected to the substrate and a second area doped in a second conductive type. In the first TFET, the second electrode serves as a source electrode, while the first electrode acts as a drain electrode. Conversely, in the second TFET, the first electrode is the source electrode, and the second electrode is the drain electrode.

Another notable patent pertains to a group III-V compound semiconductor nanowire. This invention is designed for use in a group III-V compound semiconductor MOSFET (FET) that operates at a small subthreshold of 100 mV/dec or less. The side face of the nanowire is a (-110) plane, which is constituted of a very small (111) plane. The nanowire features a first layer with a (111)A plane as a side face and a second layer with a (111)B plane as a side face. These layers are stacked alternately in the axial direction, showcasing the innovative design of his semiconductor technology.

Career Highlights

Katsuhiro Tomioka has worked with esteemed institutions such as Hokkaido University and the Japan Science and Technology Agency. His experience in these organizations has allowed him to develop and refine his innovative ideas in semiconductor technology.

Collaborations

Throughout his career, Tomioka has collaborated with notable colleagues, including Takashi Fukui and Junichi Motohisa. These partnerships have contributed to the advancement of his research and inventions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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