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For the Inventor, By the Inventor

Fremont, CA, United States of America

Kashmir S Sahota

This inventor holds 42 USPTO granted patents and 1 EPO patent, primarily in Semiconductor Manufacturing. Top assignees: Advanced Micro Devices Corporation, Spansion LLC.. Active years: 1991-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kashmir S Sahota. Retrieved from https://idiyas.com/inventor/kashmir-s-sahota

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 42

% Patents Active = 73.8


Average Co-Inventor Count = 2.9

ph-index = 12

Forward Citations = 526(Granted Patents)


Location History:

  • Union City, CA (US) (1991)
  • Fremont, CA (US) (1997 - 2013)

Company Filing History:

goldMedal39 out of 13,175 
 
Advanced Micro Devices Corporation
 patents
silverMedal5 out of 1,075 
 
Spansion LLC.
 patents
where one patent can have more than one assignee

Years Active: 1991-2013

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Areas of Expertise:
Memory Cell Fabrication
Chemical-Mechanical Polishing
Interconnect Materials
Trench Isolation
Dielectric Coatings
Silicon Integrated Circuits
Wafer Planarization
Conductivity Regions
Polysilicon Defects
Array Erosion
Photoresist Techniques
High-Performance Semiconductors
42 patents (USPTO):Explore Patents
1. 8384146 - Methods for forming a memory cell having a top oxide spacer (2013-02-26),
2. 8202779 - Methods for forming a memory cell having a top oxide spacer (2012-06-19),
3. 7449413 - Method for effectively removing polysilicon nodule defects (2008-11-11),
4. 7358191 - Method for decreasing sheet resistivity variations of an interconnect metal layer (2008-04-15),
5. 7307002 - Non-critical complementary masking method for poly-1 definition in flash memory device fabrication (2007-12-11),
6. 7294573 - Method for controlling poly 1 thickness and uniformity in a memory array fabrication process (2007-11-13),
7. 7208382 - Semiconductor device with high conductivity region using shallow trench (2007-04-24),
8. 7141502 - Slurry-less polishing for removal of excess interconnect material during fabrication of a silicon integrated circuit (2006-11-28),
9. 7077728 - Method for reducing edge array erosion in a high-density array (2006-07-18),
10. 7053446 - Memory wordline spacer (2006-05-30),
11. 7052969 - Method for semiconductor wafer planarization by isolation material growth (2006-05-30),
12. 6927113 - Semiconductor component and method of manufacture (2005-08-09),
13. 6773988 - Memory wordline spacer (2004-08-10),
14. 6770523 - Method for semiconductor wafer planarization by CMP stop layer formation (2004-08-03),
15. 6723605 - Method for manufacturing memory with high conductivity bitline and shallow trench isolation integration (2004-04-20),

Title: The Innovative Mind of Kashmir S Sahota

Introduction: Kashmir S Sahota is a pioneering inventor based in Fremont, California. Her groundbreaking work in the field of technology has earned her recognition as a leading figure in the industry.

Latest Patents: Kashmir S Sahota holds several patents in various technological fields, including artificial intelligence, renewable energy, and biotechnology. Her innovative solutions have revolutionized the way we approach complex problems in these areas.

Career Highlights: With a career spanning over two decades, Kashmir S Sahota has worked with some of the top research institutions and tech companies in the world. Her contributions have led to significant advancements in cutting-edge technologies.

Collaborations: Throughout her career, Kashmir S Sahota has collaborated with renowned scientists, engineers, and researchers to bring her ideas to life. These collaborations have resulted in the development of groundbreaking products and technologies.

Conclusion: Kashmir S Sahota's passion for innovation and relentless pursuit of excellence continue to inspire the next generation of inventors. Her impact on the tech industry is undeniable, and her legacy will undoubtedly shape the future of technology for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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