The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 10, 2004
Filed:
Sep. 13, 2002
Applicant:
Inventors:
Kashmir S. Sahota, Fremont, CA (US);
Tazrien Kamal, San Jose, CA (US);
Mark T. Ramsbey, Sunnyvale, CA (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18234 ; H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/18234 ; H01L 2/1336 ;
Abstract
A manufacturing method for a memory and a memory made thereby includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited and formed. A doped wordline spacer layer is deposited and a doped wordline spacer is formed adjacent to the wordline.
Sahota, Kashmir. (2004). Memory wordline spacer (U.S. Patent No. 6773988). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6773988
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile