Edison, NJ, United States of America

Kannan Rajamani

This inventor holds 18 USPTO granted patents and 5 published patent applications, primarily in Digital Signal Processing. Top assignees: Intel Corporation, Agere Systems Inc., Agere Systems Guardian Corp.. Active years: 2001-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kannan Rajamani. Retrieved from https://idiyas.com/inventor/kannan-rajamani

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 18 

% Patents Active = 88.9

Average Co-Inventor Count = 3.4

ph-index = 5

Forward Citations = 66(Granted Patents)


Location History:

  • Tinton Falls, NJ (US) (2001 - 2004)
  • Edison, NJ (US) (2003 - 2024)

Company Filing History:


Years Active: 2001-2026

Loading Chart...
Areas of Expertise:
Crest Factor Reduction
Digital Pre-Distortion
Analog-to-Digital Converter
Hybrid Hardware Accelerator
Data Synchronization
Echo Cancellation
Transceiver Design
Sample Rate Conversion
Real Time Tuner
Modem Technology
Digital Filters
18 patents (USPTO):Explore Patents

Title: The Innovative Mind of Kannan Rajamani

Introduction

Kannan Rajamani is a prominent inventor based in Edison, NJ, known for his significant contributions to technology and engineering. With a total of 13 patents to his name, he has made a remarkable impact in the field of digital signal processing and hardware architecture.

Latest Patents

One of his latest patents is focused on digital pre-distortion (DPD) adaptation using a hybrid hardware accelerator and programmable array architecture. This innovation discloses techniques for utilizing a hybrid architecture that combines a programmable processing array with a hardware accelerator. The architecture dedicates the most computationally intensive blocks to the hardware accelerator, which is implemented for the computation of pre-distortion coefficients. This design maintains flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, achieving a division of functionality while connecting the components without sacrificing flexibility. This results in a balance between power, area, and flexibility.

Another notable patent by Rajamani is the hybrid hardware accelerator and programmable array architecture. Similar to his previous work, this patent emphasizes the use of a hybrid architecture that combines a programmable processing array with a hardware accelerator. The architecture dedicates the most computationally intensive blocks to the hardware accelerator while allowing for additional computations to be performed by the programmable processing array. The interface for coupling these components is designed to maintain functionality and flexibility, further enhancing the efficiency of the system.

Career Highlights

Throughout his career, Kannan Rajamani has worked with leading technology companies, including Agere Systems Inc. and Intel Corporation. His experience in these organizations has allowed him to develop and refine his innovative ideas, contributing to advancements in the industry.

Collaborations

Kannan has collaborated with notable professionals in his field, including Yhean-Sen Lai and Bahman Barazesh. These collaborations have fostered an environment of innovation and creativity, leading to the development of groundbreaking technologies.

Conclusion

Kannan Rajamani's contributions to technology through his patents and collaborations highlight his innovative spirit and dedication to advancing the field. His work continues to influence the landscape of digital signal processing and hardware architecture.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…