Agere Systems Inc.

Intel Corporation

Agere Systems Guardian Corp.

Kannan Rajamani

Yhean-Sen Lai

Bahman Barazesh

Raja Banerjea

Kameran Azadet

Zoran Zivkovic

Thomas Smith

Albert Molina

Matteo Camponeschi

Cecil William Farrow

Martin Clara

Christian Lindholm

Ramon Sanchez

Tony S El-Kik

Giacomo Cascio

Steven C Szep

Kevin Kinney

Geoffrey Lawrence Smith

Kevin R Kinney

Tomasz Janusz Wolak

Nitin Kumar Varma

An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.

Analog-to-digital converter system, receiver, base station, mobile device and method for analog-to-digital conversion

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted and a measured or observed transmission of the data samples. By comparing these blocks of data samples, DFE functions such as digital pre-distortion (DPD) parameter adaptation may be implemented. The hybrid architecture enables high flexibility at low additional cost. To further limit the costs, the programable processing array may have processing power and memory that is reduced compared to conventional processing array implementations.

Data synchronization techniques for a hybrid hardware accelerator and programmable processing array architecture

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, which may be implemented for the computation of pre-distortion (DPD) coefficients while maintaining flexibility for additional DPD computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

Digital pre-distortion (DPD) adaptation using a hybrid hardware accelerator and programmable array architecture

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture dedicates the most computationally intensive blocks to the hardware accelerator, while maintaining flexibility for additional computations to be performed by the programmable processing array. An interface is also described for coupling the processing array to the hardware accelerator, which achieves a division of functionality and connects the programmable processing array components to the hardware accelerator components without sacrificing flexibility. This results in a balance between power/area and flexibility.

Hybrid hardware accelerator and programmable array architecture

A method and system for controlling an analog-to-digital converter (ADC) in an observation path in a transceiver. The transceiver includes a transmit path, a receive path, and an observation path. The observation path includes an analog buffer and an observation ADC. A controller generates a control signal to control sampling events at the observation ADC to activate the observation ADC at combined uniform and non-uniform sampling instants. The controller may also generate a second control signal indicating whether digital data obtained by the observation ADC is valid or not. The digital data generated by the observation ADC at non-uniform sampling instants is indicated as invalid and digital data generated by the observation ADC at uniform sampling instants is indicated as valid. The digital data indicated as invalid may be discarded and the digital data indicated as valid is used for calibration of the transmit path or the receive path.

Transceiver and method and system for controlling an analog-to-digital converter in an observation path in the transceiver

One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.

De-interleaving on an as-needed basis

A unique real time tuning (RTT) process is employed for obtaining the desired optimum device parameter adjustments. The RTT parameter adjustment process is utilized with IP phone or other device chipsets as desired. In one embodiment, RTT provides a graphical user interface to a digital signal processor (DSP), or the like, on the device chipset allowing for observation, evaluation and control of the device parameters in real time. The real time exchange of the device parameter information between the device and an external workstation, e.g., a personal computer or the like, is provided by a User Datagram Protocol (UDP) that runs on a controller on the device, e.g., an ARM processor or the like. In this example, the unique combination of the RTT, UDP and DSP cooperate advantageously to implement, in accordance with the principles of the invention, the desired observability, and control to designers to tune the device, e.g., IP Phone, in real time to specified hardware, plastics, audio requirements required by existing standards or the like.

Real time tuner for providing graphical user interface

Apparatus and devices used to achieve a computationally efficient modem having a transmit path and a receive path. The apparatuses include a Farrow phase shifter for shifting the phase of signals in the transmit path, a fractionally spaced equalizer capable of equalization and signal decimation in the receive path, a primary echo sub-canceler and a post equalizer echo canceler for canceling echoes on the receive path, and a phase locked loop and add/delete register for controlling the sampling rate of a CODEC. The method includes shifting the phase of a transmit signal using a Farrow structure, equalizing and decimating a receive signal with a fractionally spaced equalizer, canceling primary echoes on the receive signal using a sub-canceler structure and canceling remaining echoes using a post equalizer echo canceler, and adjusting the sampling rate of a CODEC using a phase locked loop and an add/delete register.

Efficient PCM modem

A modem incorporating apparatus and methods to achieve computationally efficient echo cancellation. The apparatus include a cyclic echo synthesizer sub-canceler in the time domain and a echo canceler in the frequency domain. The method includes generating a cyclic echo synthesizer signal using a sub-canceler structure, adding the cyclic echo synthesizer signal to a receive signal in the time domain, generating an echo cancellation signal, and subtracting the echo cancellation signal from the receive signal in the frequency domain. The apparatus and methods may be used for echo cancellation in an asynchronous digital subscriber line (ADSL) modem using discrete multi-tone (DMT) technology.

Modem with enhanced echo canceler

A circuit compensating for the difference in transmission rate of digital samples generated in transmit and receive paths between a user and a transceiver processing in the frequency domain, such as a digital multi-tone (DMT) transceiver. Compensation of the DMT transmission rate in the receive path in accordance with exemplary embodiments of the present employs zero-padding of the frequency domain coefficients generated by the DMT transceiver prior to applying an inverse transform, such as the inverse fast Fourier transform (IFFT). Zero-padding the frequency domain coefficients allows for the compensation of the transmission rate in the receive path by generating digital samples from the frequency domain coefficients with an inverse transform having a rate matched to the frequency domain transform and rate employed in the transmit path.

Transmission rate compensation for a digital multi-tone transceiver

A DMT signal conforming to a first DMT standard (e.g., the full-rate G.dmt standard based on 255 tones) is sampled at a sampling rate for the first DMT standard, filtered to attenuate a subset of the tones of the first DMT standard (e.g., all G.dmt tones above tone &num;127), and subsampled (e.g., 2:1) to provide a subsampled, filtered signal that can be further processed using components designed to operate under a second, different DMT standard (e.g., the half-rate G.lite standard based on 127 tones). As such, a conventional half-rate G.lite DMT transceiver can be modified (e.g., by changing the downstream sampling rate from 1.104 MHz to 2.208 MHz and adding an appropriate low-pass filter and decimator) for configuration in a full-rate G.dmt DMT system. The filtering and subsampling ensure that a downstream signal (even if it is a full-rate DMT initialization or synchronization signal containing tones above tone &num;127) can successfully be further processed using conventional half-rate DMT transceiver components, which are less complex and less expensive than those of full-rate DMT transceivers, thereby enabling the use of relatively inexpensive consumer personal equipment (CPE) in existing distributed full-rate DMT telecommunications systems.

Low-complexity DMT transceiver

A method of converting between a sampling rate associated with a first audio format and a second audio format includes up-sampling an input signal sampled at the sample rate associated with the first audio format. Then, the up-sampled signal is filtered as a function of a fractional delay to generate an output signal sampled at the sample rate associated with the second audio format. The fractional delay is computed from the sample rates associated with the first and second audio formats. In one embodiment, the sample rates that are converted between are associated with a compact disc format having a sample rate of about 44.1 kHz and a digital audio tape format having a sample rate of about 48 kHz. In such case, the input samples are preferably up-sampled by a factor of two and the samples are then preferably filtered in accordance with a third order six taps coefficient finite impulse response filtering technique. The methodology of the present invention permits sample rate conversion from the CD format to the DAT format and from the DAT format to the CD format without changing filter coefficients.

Methods and apparatus for providing sample rate conversion between CD and DAT

A pulse code modulation modem having a far echo canceller that compensates for robbed bit echo noise by polling the receiving modem for robbed bit position information and incorporating that information into its far echo cancellation circuitry.

Far echo canceller for PCM modems

A method for designing an all pass filter, in accordance with the present invention, includes providing a plurality of signals having a group delay, and normalizing the group delay to determine a normalized group delay function. Cepstral coefficients of the normalized group delay function are determined for to a denominator polynomial of a transfer function of the all pass filter wherein a magnitude function and the normalized group delay function of the denominator polynomial are related through the cepstral coefficients. The denominator polynomial coefficients are determined through a non-linear recursive difference equation by employing the cepstral coefficients.

Method for designing all pass digital filters

A so-called post equalization echo canceler is utilized in conjunction with transmitter and receiver data timing synchronization to enhance tracking of the echo path impulse response and convergence of the transversal filter in the post equalization echo canceler. This is realized by employing the equalization error in the receiver to adapt coefficients of the post equalization echo canceler transversal filter, in conjunction, with the transmitter and receiver data timing synchronization. The timing synchronization is realized by using sample rate conversion of the transmit sample rate to the receive sample rate and, in one example, variable phase interpolation of the converted timing signal. The receiver timing is recovered, and a phase error signal generated by the timing recovery unit is advantageously employed to adjust a variable phase interpolator in the receiver and a variable phase interpolator in a path supplying the transmitter signal to an input of the post equalization echo canceler. This insures that both the adaptive transversal filter of the post equalization echo canceler and a transversal filter in an equalizer in the receiver are operating on data having the same timing. In this example, the timing is that of the received data signal. In an embodiment of the invention, the post equalization echo canceler is utilized in conjunction with a so-called conventional, e.g., a primary, echo canceler. The conventional echo canceler is employed before the equalizer to cancel a major portion of any echo signal, while the post equalization echo canceler is employed after the equalizer to cancel residual echo signals caused primarily by drift in the hybrid network. To this end, the conventional echo canceler is &ldquo;trained&rdquo; during the initial half-duplex operation of the modem and, then, updating of its impulse response is inhibited, while the post equalization echo canceler is allowed to continue adapting.

Growing community of inventors

Edison, NJ, United States of America

Kannan Rajamani