The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 04, 2026

Filed:

Dec. 29, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kannan Rajamani, Basking Ridge, NJ (US);

Kameran Azadet, San Ramon, CA (US);

Kevin Kinney, Coopersburg, PA (US);

Thomas Smith, Colmar, PA (US);

Zoran Zivkovic, Hertogenbosch, NL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/04 (2006.01); H04L 25/03 (2006.01); G06F 9/50 (2006.01); G06F 9/54 (2006.01); G06F 15/80 (2006.01);
U.S. Cl.
CPC ...
H04B 1/0475 (2013.01); H04L 25/03343 (2013.01); G06F 9/5027 (2013.01); G06F 9/54 (2013.01); G06F 15/80 (2013.01); H04B 2001/0425 (2013.01);
Abstract

Techniques are disclosed for the use of a hybrid architecture that combines a programmable processing array and a hardware accelerator. The hybrid architecture functions to maintain synchronization between data samples to be transmitted, feedback data samples measured from an observed previous transmission of data samples, and output data samples that comprise the data samples from previous data transmissions, which may include data samples prior to or after the application of DPD terms. The architecture enables synchronization amongst several transmission channels, and provides for high flexibility with respect to timing flows and the movement and processing of data blocks.


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