The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Matteo Camponeschi, Villach, AT;

Albert Molina, Novelda, ES;

Kannan Rajamani, Basking Ridge, NJ (US);

Martin Clara, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/10 (2006.01); H03M 1/18 (2006.01);
U.S. Cl.
CPC ...
H03M 1/0609 (2013.01); H03M 1/1042 (2013.01); H03M 1/188 (2013.01);
Abstract

An analog-to-digital converter (ADC) system is provided. The ADC system includes a first signal path. The first signal path includes a first ADC configured to generate first digital data based on an input signal. The first ADC is a time-interleaved ADC including a plurality of sub-ADCs. The first signal path further includes circuitry configured to output activity data indicating at least which of the plurality of sub-ADCs is currently active. The ADC system further includes a correction circuit configured to output digital correction data based on the activity data. Further, the ADC system includes a second signal path coupled in parallel to the first signal path. The second signal path includes a second ADC configured to generate second digital data based on the input signal and a combiner circuit configured to generate modified second digital data by combining the second digital data and the correction data. The ADC system further includes an equalizer configured to generate an equalized output signal of the ADC system based on the first digital data. The equalizer is configured to adjust, based on the modified second digital data, at least one equalization parameter used for generating the equalized output signal of the ADC system.


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