Wappingers Falls, NY, United States of America

Kamalesh K Srivastava

This inventor holds 38 USPTO granted patents and 1 published patent application, primarily in Solder Interconnects. Top assignees: International Business Machines Corporation, Tessera Intellectual Properties, Inc., Ultratech, Inc.. Active years: 1991-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kamalesh K Srivastava. Retrieved from https://idiyas.com/inventor/kamalesh-k-srivastava

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 38 (Patent Applications = 1)

% Patents Active = 73.7

Average Co-Inventor Count = 5.8

ph-index = 9

Forward Citations = 553(Granted Patents)

Location History:

Wappinger Falls, NY (US) (1998)
Wapperings Falls, NY (US) (2016)
Wappingers Falls, NY (US) (1991 - 2022)

Company Filing History:

36 out of 166,425

International Business Machines Corporation

patents

1 out of 1

Tessera Intellectual Properties, Inc.

Years Active: 1991-2022

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Areas of Expertise:

Multilayer Pillar

Lead-Free Solder

Solder Interconnects

Flip-Chip Assembly

Grain Fragmentation

Metallurgical Properties

Bond Pad Formation

Dual Damascene

Conductive Encapsulation

Reactive Ion Etching

Power Distribution

Palladium Soldering

38 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11244917 - Multilayer pillar for reduced stress interconnect and method of making same (2022-02-08),

2. 11171102 - Multilayer pillar for reduced stress interconnect and method of making same (2021-11-09),

3. 11094657 - Multilayer pillar for reduced stress interconnect and method of making same (2021-08-17),

4. 10403590 - Multilayer pillar for reduced stress interconnect and method of making same (2019-09-03),

5. 10396051 - Multilayer pillar for reduced stress interconnect and method of making same (2019-08-27),

6. 9640501 - Multilayer pillar for reduced stress interconnect and method of making same (2017-05-02),

7. 9472520 - Multilayer pillar for reduced stress interconnect and method of making same (2016-10-18),

8. 9111816 - Multilayer pillar for reduced stress interconnect and method of making same (2015-08-18),

9. 8910853 - Additives for grain fragmentation in Pb-free Sn-based solder (2014-12-16),

10. 8493746 - Additives for grain fragmentation in Pb-free Sn-based solder (2013-07-23),

11. 8314500 - Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers (2012-11-20),

12. 8293587 - Multilayer pillar for reduced stress interconnect and method of making same (2012-10-23),

13. 8197612 - Optimization of metallurgical properties of a solder joint (2012-06-12),

14. 7952207 - Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening (2011-05-31),

15. 7932169 - Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers (2011-04-26),

Title: Inventor Kamalesh K Srivastava - Pioneering Innovations in Wappingers Falls

Introduction: Kamalesh K Srivastava is a distinguished inventor based in Wappingers Falls, NY, known for his groundbreaking contributions to various technological fields.

Latest Patents: Kamalesh K Srivastava holds several patents in the areas of renewable energy, nanotechnology, and medical devices, showcasing his versatility and ingenuity in the realm of innovation.

Career Highlights: With a career spanning over two decades, Srivastava has worked with leading research institutions and companies, consistently pushing the boundaries of scientific discovery and technological advancement.

Collaborations: Throughout his career, Kamalesh K Srivastava has collaborated with top-tier universities, multinational corporations, and renowned inventors, fostering a culture of innovation and knowledge exchange.

Conclusion: Inventor Kamalesh K Srivastava's relentless pursuit of innovation and his commitment to pushing the boundaries of technology make him a true pioneer in the field of inventions.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

1 patent pending: