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For the Inventor, By the Inventor

San Jose, CA, United States of America

Kadthala Ramaya Narendrnath

This inventor holds 44 USPTO granted patents and 8 published patent applications and 2 EPO patents, primarily in Semiconductor Processing. Top assignee: Applied Materials, Inc.. Active years: 2000-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kadthala Ramaya Narendrnath. Retrieved from https://idiyas.com/inventor/kadthala-ramaya-narendrnath

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 44 

% Patents Active = 79.5

 

Average Co-Inventor Count = 3.6

ph-index = 14

Forward Citations = 1,006(Granted Patents)


Location History:

  • San Francisco, CA (US) (2002)
  • San Jose, CA (US) (2000 - 2023)

Company Filing History:

goldMedal44 out of 14,502 
 
Applied Materials, Inc.
 patents

Years Active: 2000-2024

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Areas of Expertise:
Electrostatic Chuck
Carrier Head Membrane
Substrate Processing
3D Printed Components
Polishing Pad
Wafer Defects
Thermal Radiation Barrier
Gas Distributor
Selective Layer Deposition
Bonding Substrates
Fluid Leakage Detection
CMP Endpoint Detection
44 patents (USPTO):Explore Patents
1. 12172264 - Carrier head membrane with regions of different roughness (2024-12-24),
2. 11826875 - Window in thin polishing pad (2023-11-28),
3. 11738421 - Method of making carrier head membrane with regions of different roughness (2023-08-29),
4. 11569069 - 3D printed chamber components configured for lower film stress and lower operating temperature (2023-01-31),
5. 11417561 - Edge ring for a substrate processing chamber (2022-08-16),
6. 11179965 - Electrostatic chuck optimized for refurbishment (2021-11-23),
7. 11161218 - Window in thin polishing pad (2021-11-02),
8. 11007619 - Carrier head membrane with regions of different roughness (2021-05-18),
9. 10777391 - 3D printed chamber components configured for lower film stress and lower operating temperature (2020-09-15),
10. 10636690 - Laminated top plate of a workpiece carrier in micromechanical and semiconductor processing (2020-04-28),
11. 10553473 - Edge ring for a substrate processing chamber (2020-02-04),
12. 10399202 - Retaining ring for lower wafer defects (2019-09-03),
13. 10213894 - Method of placing window in thin polishing pad (2019-02-26),
14. 10177014 - Thermal radiation barrier for substrate processing chamber components (2019-01-08),
15. 10160093 - Carrier head membrane roughness to control polishing rate (2018-12-25),

Title: Inventor Kadthala Ramaya Narendrnath

Introduction: Kadthala Ramaya Narendrnath is a pioneering inventor based in San Jose, CA, known for her groundbreaking contributions to the field of technology and innovation.

Latest Patents: Kadthala Ramaya Narendrnath holds several patents in the areas of artificial intelligence, machine learning, and renewable energy technologies.

Career Highlights: With a career spanning over two decades, Kadthala Ramaya Narendrnath has worked with leading tech companies, research institutions, and universities to develop cutting-edge solutions that have revolutionized various industries.

Collaborations: Throughout her career, Kadthala Ramaya Narendrnath has collaborated with top engineers, scientists, and researchers to bring her innovative ideas to life. Her collaborative efforts have resulted in numerous successful projects and patents.

Conclusion: Kadthala Ramaya Narendrnath's passion for innovation and her relentless pursuit of excellence have solidified her reputation as a visionary inventor in the tech world. Her contributions continue to inspire the next generation of inventors and innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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