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Taichung, Taiwan

Jyun-Hong Chen

This inventor holds 14 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2014-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jyun-Hong Chen. Retrieved from https://idiyas.com/inventor/jyun-hong-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 14

% Patents Active = 92.9

Average Co-Inventor Count = 5.0

ph-index = 3

Forward Citations = 139(Granted Patents)


Location History:

  • Taichung, TW (2014 - 2024)
  • Hsinchu, TW (2023 - 2024)

Company Filing History:

goldMedal14 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2014-2025

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14 patents (USPTO):Explore Patents
1. 12400987 - Semiconductor device (2025-08-26),
2. 12374572 - Systems and methods for systematic physical failure analysis (PFA) fault localization (2025-07-29),
3. 12027396 - Systems and methods for systematic physical failure analysis (PFA) fault localization (2024-07-02),
4. 12021050 - Semiconductor device (2024-06-25),
5. 11681851 - Hierarchical density uniformization for semiconductor feature surface planarization (2023-06-20),
6. 11669957 - Semiconductor wafer measurement method and system (2023-06-06),
7. 11600505 - Systems and methods for systematic physical failure analysis (PFA) fault localization (2023-03-07),
8. 11469198 - Semiconductor device manufacturing method and associated semiconductor die (2022-10-11),
9. 11182532 - Hierarchical density uniformization for semiconductor feature surface planarization (2021-11-23),
10. 11094057 - Semiconductor wafer measurement method and system (2021-08-17),
11. 10762621 - Semiconductor wafer measurement method and system (2020-09-01),
12. 10304178 - Method and system for diagnosing a semiconductor wafer (2019-05-28),
13. 9230867 - Structure and method for E-beam in-chip overlay mark (2016-01-05),
14. 8736084 - Structure and method for E-beam in-chip overlay mark (2014-05-27),

Title: Innovations of Jyun-Hong Chen

Introduction

Jyun-Hong Chen is a prominent inventor based in Taichung, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 14 patents. His work focuses on enhancing the efficiency and reliability of semiconductor devices.

Latest Patents

One of his latest patents involves a semiconductor device that includes a first formation site and a second formation site for forming conductive bumps. This invention addresses the environmental density around these sites, optimizing their design for better performance. Another notable patent is related to systematic physical failure analysis (PFA) fault localization. This patent outlines systems and methods that utilize computational GDS-assisted navigation to accelerate physical fault analysis, helping to identify systematic fault locations and patterns effectively.

Career Highlights

Jyun-Hong Chen is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His innovative work has contributed to the advancement of semiconductor technologies, making a lasting impact on the field.

Collaborations

He has collaborated with notable colleagues such as Wen-Hao Cheng and Peng-Ren Chen, further enhancing the scope and impact of his inventions.

Conclusion

Jyun-Hong Chen's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence advancements in semiconductor devices and fault analysis methods.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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