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For the Inventor, By the Inventor

Chi Shange Town, Kaoshung County, Taiwan

Juing-Yi Cheng

This inventor holds 8 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2002-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Juing-Yi Cheng. Retrieved from https://idiyas.com/inventor/juing-yi-cheng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 8

% Patents Active = 75.0

Average Co-Inventor Count = 2.3

ph-index = 5

Forward Citations = 140(Granted Patents)


Location History:

  • Chishang Town, Kaoshing County, TW (2002)
  • Kaoshung County, TW (2003)
  • Chi Shange, TW (2003)
  • Chishang town, TW (2003)
  • Kaoshung, TW (2004)
  • Chi-Shan Jen, TW (2004)
  • Chi-Shan, TW (2006)
  • Chi Shange Town, Kaoshung County, TW (2006)

Company Filing History:

goldMedal8 out of 42,926 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2002-2006

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8 patents (USPTO):Explore Patents
1. 7087528 - Chemical-mechanical polishing (CMP) process for shallow trench isolation (2006-08-08),
2. 7087508 - Method of improving short channel effect and gate oxide reliability by nitrogen plasma treatment before spacer deposition (2006-08-08),
3. 6821868 - Method of forming nitrogen enriched gate dielectric with low effective oxide thickness (2004-11-23),
4. 6743715 - Dry clean process to improve device gate oxide integrity (GOI) and reliability (2004-06-01),
5. 6649538 - Method for plasma treating and plasma nitriding gate oxides (2003-11-18),
6. 6638866 - Chemical-mechanical polishing (CMP) process for shallow trench isolation (2003-10-28),
7. 6541382 - Lining and corner rounding method for shallow trench isolation (2003-04-01),
8. 6391792 - Multi-step chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layer (2002-05-21),

Title: Juing-Yi Cheng: Innovator in Semiconductor Technology

Introduction

Juing-Yi Cheng is a prominent inventor based in Chi Shange Town, Kaoshung County, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 8 patents. His work focuses on improving processes that enhance the reliability and efficiency of semiconductor devices.

Latest Patents

One of his latest patents is a chemical-mechanical polishing (CMP) process for shallow trench isolation. This method involves etching trenches through various layers and filling them with an oxide layer. A silicon oxynitride layer is then deposited and polished away using a first slurry with high selectivity, followed by a second polishing to remove the oxide layer with a second slurry of low selectivity. Additionally, he has developed a method for improving short channel effect and gate oxide reliability through nitrogen plasma treatment before spacer deposition. This innovative approach enhances the manufacturing of gate electrodes by eliminating defects in the silicon substrate and gate electrode sidewalls.

Career Highlights

Juing-Yi Cheng is currently employed at Taiwan Semiconductor Manufacturing Company Ltd., where he continues to advance semiconductor technologies. His expertise in chemical-mechanical polishing and plasma treatment has positioned him as a key figure in the industry.

Collaborations

He has collaborated with notable coworkers, including Syun-Ming Jang and Kevin Su, contributing to various innovative projects within the semiconductor field.

Conclusion

Juing-Yi Cheng's contributions to semiconductor technology through his patents and innovative methods have significantly impacted the industry. His work continues to pave the way for advancements in semiconductor manufacturing processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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