Niles, IL, United States of America

Joseph V Cesna

This inventor holds 21 USPTO granted patents, primarily in Wafer Polishing. Top assignees: Speedfam Corporation, Speedfam-Ipec Corporation, Speedram Corporation. Active years: 1981-2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Joseph V Cesna. Retrieved from https://idiyas.com/inventor/joseph-v-cesna

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 1.4

ph-index = 12

Forward Citations = 475(Granted Patents)


Location History:

  • Niles, IL (US) (1981 - 2001)
  • Nlles, IL (US) (2001)

Company Filing History:


Years Active: 1981-2001

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Areas of Expertise:
Wafer Polishing
Surface Treatment
Endpoint Detection
Flatness Control
Grinding Stones
Polishing Pads
Abrasive Machines
Planarization
Dual Column Abrading
Conditioning Devices
Microsize Wafers
Pressure Plate
21 patents (USPTO):Explore Patents

Title: Joseph V Cesna: Innovator in Surface Treatment Technologies

Introduction

Joseph V Cesna, based in Niles, IL, has made significant contributions to the field of surface treatment technologies through his 21 patents. His inventive work has introduced advanced methodologies and apparatuses that are essential in the polishing and planarizing of workpieces, particularly in the semiconductor industry.

Latest Patents

Among his notable patents is the innovative "Methods and apparatus for improved polishing of workpieces." This apparatus includes a polishing pad designed with a unique array of self-cleaning and anti-tracking grooves. These features guide slurry and polishing debris effectively across the pad's surface, minimizing localized wear zones. Notably, the grooves display a concentric pattern and are crafted with a compound shape, integrating both vertical and sloped surfaces for optimal functionality.

Another recent patent is the "Apparatus and method for the face-up surface treatment of wafers." This invention features an indexing table capable of holding multiple semiconductor wafers. Each position on the table accommodates different surface treatment arrangements, allowing for a synchronized loading and unloading process. The progress of each wafer's surface treatment can be monitored, with options to modify subsequent steps to achieve the desired substrate condition.

Career Highlights

Joseph V Cesna's career includes significant tenures at reputable firms such as Speedfam Corporation and Speedfam-IPEC Corporation. His work at these companies has been pivotal in advancing polishing and surface treatment solutions, reflecting his commitment to innovation and quality in the industry.

Collaborations

Throughout his career, Joseph has collaborated with prominent colleagues including Inki Kim and Lawrence O. Day. These partnerships have fostered a collaborative environment that enhances the development of cutting-edge technologies in surface treatment.

Conclusion

Joseph V Cesna stands out as a prominent inventor in the realm of surface treatment technologies. His innovative patents and collaborations have not only advanced industry standards but also paved the way for future innovations in the field. With a fruitful career dedicated to improving workpiece polishing methods and apparatuses, Cesna's contributions will continue to impact both existing and emerging technological landscapes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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