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For the Inventor, By the Inventor

Hospitalet de Llobregat, Spain

Josep M Codina

USPTO Granted Patents = 12 

Average Co-Inventor Count = 7.5

ph-index = 4

Forward Citations = 63(Granted Patents)


Location History:

  • Llobregat, ES (2013)
  • Hospitalet de Llobregat, ES (2011 - 2018)
  • L'Hospitalet del Llobregat, ES (2018)
  • Barcelona, ES (2014 - 2020)

Company Filing History:

goldMedal12 out of 54,664 
 
Intel Corporation
 patents

Years Active: 2011-2020

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12 patents (USPTO):Explore Patents
1. 10621092 - Merging level cache and data cache units having indicator bits related to speculative execution (2020-04-14),
2. 10157063 - Instruction and logic for optimization level aware branch prediction (2018-12-18),
3. 10013326 - Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region (2018-07-03),
4. 9983880 - Method and apparatus for improved thread selection (2018-05-29),
5. 9940138 - Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations (2018-04-10),
6. 9811341 - Managed instruction cache prefetching (2017-11-07),
7. 8909902 - Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution (2014-12-09),
8. 8898646 - Method and apparatus for flexible, accurate, and/or efficient code profiling (2014-11-25),
9. 8612698 - Replacement policy for hot code detection (2013-12-17),
10. 8261046 - Access of register files of other threads using synchronization (2012-09-04),
11. 8190652 - Achieving coherence between dynamically optimized code and original code (2012-05-29),
12. 7895415 - Cache sharing based thread control (2011-02-22),
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