The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2011
Filed:
Feb. 14, 2007
Antonio Gonzalez, Barcelona, ES;
Josep M. Codina, Hospitalet de Llobregat, ES;
Pedro Lopez, Molins de Rei, ES;
Fernando Latorre, Huesca, ES;
Jose-alejandro Pineiro, Barcelona, ES;
Enric Gibert, Sant Cugat del Vallès, ES;
Jaume Abella, Barcelona, ES;
Jaideep Moses, Portland, OR (US);
Donald Newell, Portland, OR (US);
Ravishankar Iyer, Portland, OR (US);
Ramesh G. Illikkal, Portland, OR (US);
Srihari Makineni, Portland, OR (US);
Antonio Gonzalez, Barcelona, ES;
Josep M. Codina, Hospitalet de Llobregat, ES;
Pedro Lopez, Molins de Rei, ES;
Fernando Latorre, Huesca, ES;
Jose-Alejandro Pineiro, Barcelona, ES;
Enric Gibert, Sant Cugat del Vallès, ES;
Jaume Abella, Barcelona, ES;
Jaideep Moses, Portland, OR (US);
Donald Newell, Portland, OR (US);
Ravishankar Iyer, Portland, OR (US);
Ramesh G. Illikkal, Portland, OR (US);
Srihari Makineni, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Apparatus and computing systems associated with cache sharing based thread control are described. One embodiment includes a memory to store a thread control instruction and a processor to execute the thread control instruction. The processor is coupled to the memory. The processor includes a first unit to dynamically determine a cache sharing behavior between threads in a multi-threaded computing system and a second unit to dynamically control the composition of a set of threads in the multi-threaded computing system. The composition of the set of threads is based, at least in part, on thread affinity as exhibited by cache-sharing behavior. The thread control instruction controls the operation of the first unit and the second unit.