The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Sep. 26, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rekai Gonzalez-Alberquilla, L'Hospitalet de Llobregat, ES;

Tanausu Ramirez, Barcelona, ES;

Josep M. Codina, L'Hospitalet del Llobregat, ES;

Enric Gibert Codina, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01); G06F 9/48 (2006.01); G06F 12/10 (2016.01); G06F 12/1027 (2016.01); G06F 12/1036 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3851 (2013.01); G06F 9/3824 (2013.01); G06F 9/3836 (2013.01); G06F 9/3855 (2013.01); G06F 9/3867 (2013.01); G06F 9/4881 (2013.01); G06F 12/1027 (2013.01); G06F 12/1036 (2013.01); G06F 2212/68 (2013.01); G06F 2212/684 (2013.01);
Abstract

An apparatus and method are described for improved thread selection. For example, one embodiment of a processor comprises: first logic to maintain a history table comprising a plurality of entries, each entry in the table associated with an instruction and including history data indicating prior hits and/or misses to a cache level and/or a translation lookaside buffer (TLB) for that instruction; and second logic to select a particular thread for execution at a particular processor pipeline stage based on the history data.


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