The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Apr. 08, 2009
Applicants:

Pedro Lopez, Molins de Rei, ES;

Carlos Madriles, Barcelona, ES;

Alejandro Martinez, Barcelona, ES;

Raul Martinez, Barcelona, ES;

Josep M. Codina, Hospitalet de Llobregat, ES;

Enric Gibert Codina, Sant Cugat del Vallès, ES;

Fernando Latorre, Barcelona, ES;

Antonio Gonzalez, Barcelona, ES;

Inventors:

Pedro Lopez, Molins de Rei, ES;

Carlos Madriles, Barcelona, ES;

Alejandro Martinez, Barcelona, ES;

Raul Martinez, Barcelona, ES;

Josep M. Codina, Hospitalet de Llobregat, ES;

Enric Gibert Codina, Sant Cugat del Vallès, ES;

Fernando Latorre, Barcelona, ES;

Antonio Gonzalez, Barcelona, ES;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01); G06F 11/00 (2006.01); G06F 9/38 (2018.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3863 (2013.01); G06F 9/30043 (2013.01); G06F 9/3842 (2013.01); G06F 9/3851 (2013.01); G06F 11/1402 (2013.01);
Abstract

Methods and apparatus are disclosed for using a register checkpointing mechanism to resolve multithreading mis-speculations. Valid architectural state is recovered and execution is rolled back. Some embodiments include memory to store checkpoint data. Multiple thread units concurrently execute threads. They execute a checkpoint mask instruction to initialize memory to store active checkpoint data including register contents and a checkpoint mask indicating the validity of stored register contents. As register contents change, threads execute checkpoint write instructions to store register contents and update the checkpoint mask. Threads also execute a recovery function instruction to store a pointer to a checkpoint recovery function, and in response to mis-speculation among the threads, branch to the checkpoint recovery function. Threads then execute one or more checkpoint read instructions to copy data from a valid checkpoint storage area into the registers necessary to recover a valid architectural state, from which execution may resume.


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