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For the Inventor, By the Inventor

Barcelona, Spain

Carlos Madriles

USPTO Granted Patents = 11 

 

Average Co-Inventor Count = 6.9

ph-index = 4

Forward Citations = 79(Granted Patents)


Company Filing History:

goldMedal11 out of 54,781 
 
Intel Corporation
 patents

Years Active: 2008-2020

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11 patents (USPTO):Explore Patents
1. 10621092 - Merging level cache and data cache units having indicator bits related to speculative execution (2020-04-14),
2. 10157063 - Instruction and logic for optimization level aware branch prediction (2018-12-18),
3. 10013326 - Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region (2018-07-03),
4. 9940138 - Utilization of register checkpointing mechanism with pointer swapping to resolve multithreading mis-speculations (2018-04-10),
5. 9374542 - Image signal processor with a block checking circuit (2016-06-21),
6. 9043773 - Identification and management of unsafe optimizations (2015-05-26),
7. 8909902 - Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution (2014-12-09),
8. 8898646 - Method and apparatus for flexible, accurate, and/or efficient code profiling (2014-11-25),
9. 8813057 - Branch pruning in architectures with speculation support (2014-08-19),
10. 8166282 - Multi-version register file for multithreading processors with live-in precomputation (2012-04-24),
11. 7458065 - Selection of spawning pairs for a speculative multithreaded processor (2008-11-25),

Title: The Innovative Mind of Carlos Madriles

Introduction

Carlos Madriles is a prominent inventor based in Barcelona, Spain. He has made significant contributions to the field of technology, particularly in the areas of computer architecture and optimization. With a total of 11 patents to his name, Madriles continues to push the boundaries of innovation.

Latest Patents

Madriles' latest patents include groundbreaking work on merging level cache and data cache units that utilize indicator bits related to speculative execution. This invention describes systems, methods, and apparatuses for decomposing a sequential program into multiple threads, executing these threads, and reconstructing the sequential execution of the threads. A plurality of data cache units (DCUs) store locally retired instructions of speculatively executed threads, while a merging level cache (MLC) merges data from the lines of the DCUs. Additionally, an inter-core memory coherency module (ICMC) globally retires instructions of the speculatively executed threads in the MLC. Another notable patent focuses on optimization-level aware branch prediction, detailing a computer-readable storage medium, method, and system for this purpose. In this invention, a gear level is assigned to a set of application instructions that have been optimized, which is then stored in a register of a branch prediction unit of a processor.

Career Highlights

Carlos Madriles has built a successful career at Intel Corporation, where he has been instrumental in developing advanced technologies. His work has not only enhanced the performance of processors but has also contributed to the overall efficiency of computing systems.

Collaborations

Madriles has collaborated with several talented individuals in his field, including Antonio Gonzalez and Raul Martinez. These partnerships have fostered a creative environment that encourages innovation and the sharing of ideas.

Conclusion

Carlos Madriles exemplifies the spirit of innovation through his extensive work and numerous patents. His contributions to technology continue to shape the future of computing, making him a key figure in the industry.

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