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For the Inventor, By the Inventor

San Jose, CA, United States of America

John Christian Holst

This inventor holds 37 USPTO granted patents and 3 published patent applications and 1 EPO patent, primarily in Semiconductor Memory. Top assignees: Advanced Micro Devices Corporation, Cisco Technology, Inc., Intergraph Corporation. Active years: 1994-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John Christian Holst. Retrieved from https://idiyas.com/inventor/john-christian-holst

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 37 

% Patents Active = 97.3

 

Average Co-Inventor Count = 1.8

ph-index = 15

Forward Citations = 590(Granted Patents)


Location History:

  • San Jose, CA (US) (1994 - 2012)
  • Saratoga, CA (US) (2013 - 2017)

Company Filing History:

goldMedal27 out of 13,192 
 
Advanced Micro Devices Corporation
 patents
silverMedal5 out of 21,458 
 
Cisco Technology, Inc.
 patents
bronzeMedal4 out of 142 
 
Intergraph Corporation
 patents
4. 1 out of 834,659 
Other
 patents

Years Active: 1994-2017

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Areas of Expertise:
Low-Power Circuits
Transistor Size Reduction
Robust Device Layouts
Forwarding Table Memory
Memory Interface Circuit
Dynamic Differential Logic
Redundancy Circuit
SOI Technology
MOSFET Devices
Active Power Supply Filter
Content Addressable Memory
Integrated Circuits
37 patents (USPTO):Explore Patents
1. 9583180 - Low-power row-oriented memory write assist circuit (2017-02-28),
2. 8547155 - Soft error robust low power latch device layout techniques (2013-10-01),
3. 8270399 - Crossbar apparatus for a forwarding table memory in a router (2012-09-18),
4. 7600181 - Circuit to reduce rail noise voltage spikes due to switching on an input-output bus (2009-10-06),
5. 7450438 - Crossbar apparatus for a forwarding table memory in a router (2008-11-11),
6. 7026691 - Minimizing transistor size in integrated circuits (2006-04-11),
7. 6420767 - Capacitively coupled DTMOS on SOI (2002-07-16),
8. 6376880 - High-speed lateral bipolar device in SOI process (2002-04-23),
9. 6287953 - Minimizing transistor size in integrated circuits (2001-09-11),
10. 6258642 - Use of functional memory cells as guard cells in a semiconductor memory (2001-07-10),
11. 6213869 - MOSFET-type device with higher driver current and lower steady state power dissipation (2001-04-10),
12. 6191034 - Forming minimal size spaces in integrated circuit conductive lines (2001-02-20),
13. 6188596 - Layout for semiconductor memory including multi-level sensing (2001-02-13),
14. 6157584 - Redundancy circuit and method for semiconductor memory (2000-12-05),
15. 6157244 - Power supply independent temperature sensor (2000-12-05),

Title: Innovator Spotlight: John Christian Holst - Revolutionizing Memory Circuits

Introduction:

John Christian Holst, an esteemed inventor based in San Jose, CA, has made significant contributions to the field of memory circuits with his groundbreaking innovations and patents.

Latest Patents:

Holst's latest patents include a cutting-edge "Low-power Row-oriented Memory Write Assist Circuit" for static random access memory (SRAM) and "Soft Error Robust Low Power Latch Device Layout Techniques" to reduce soft error rates caused by radiation exposure.

Career Highlights:

With an impressive portfolio of 37 patents, John Christian Holst has demonstrated his expertise in developing advanced technologies. He has worked with renowned companies such as Advanced Micro Devices (AMD) and Cisco Technologies, Inc., showcasing his versatility and innovation in the tech industry.

Collaborations:

Throughout his career, Holst has collaborated with industry experts like Asim A Selcuk and Nicholas John Kepler, further cementing his reputation as a collaborative and forward-thinking inventor.

Conclusion:

John Christian Holst's dedication to pushing the boundaries of memory circuit design has solidified his status as a visionary inventor. His contributions to the field continue to shape the future of technology, inspiring the next generation of innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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