Advanced Micro Devices Corporation

Cisco Technology, Inc.

Intergraph Corporation

Other

John Christian Holst

Stephen C Horne

Asim A Selcuk

Raymond T Lee

Nicholas John Kepler

Christopher A Spence

Richard K Klein

Craig S Sander

Donald A Draper

Dennis L Wendell

Bin Yu

William L Lynch

Amos Ben-Meir

Rich K Klein

Christoper A Spence

John Gregory Favor

Thomas H Lee

Mark G Johnson

Srinath Krishnan

Hamid Partovi

Richard J Wong

Brian Alleyne

Joseph G Nolan, Iii

ShiJie Wen

Benjamin S Wong

Hai Ngoc Nguyen

Imtiaz P Shaik

Aspects of the present disclosure generally relate to static random access memory (SRAM), and more specifically, to a low-power, row-oriented memory write assist circuit. The SRAM may generally comprise an array of bit cells arranged in rows and columns, wherein each bit cell in a row is selected for writing via a corresponding wordline for that row and wherein each bit cell in a column is coupled to a corresponding pair of bitlines for supplying complementary data values, and at least one row-oriented write assist circuit configured to temporarily reduce, to a desired voltage level, a voltage on an internal voltage line used to supply power to the bit cells of a row selected for writing.

Low-power row-oriented memory write assist circuit

A latch device and related layout techniques are provided to reduce soft error rates caused by radiation or other exposure to ionized/charged particles. The latch device comprises a pair of cross-coupled inverters forming a storage cell. A pair of clock pass transistors is coupled to the pair of cross-coupled inverters. The pair of clock pass transistors is configured to receive as input a clock signal. On both true and complement sides of the latch device, a channel-connected region is formed between one of the pair of cross-coupled inverters and one of the pair of clock pass transistors. Each channel-connected region is configured to have a reduced Linear Energy Transfer (LET) cross-section. The reduced LET cross-section results in a reduced soft error rate.

Soft error robust low power latch device layout techniques

A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a sector of the memory so that data from the sector can be read. In one example, any one of the stages of the plurality of stages may be selectively and dynamically coupled with any one of the sectors of the forwarding table memory for providing an address to a particular sector of the memory to read data therefrom.

Crossbar apparatus for a forwarding table memory in a router

A circuit to reduce noise spikes on the power and ground rails of a chip when switching over an input-output bus, the circuit comprising an encoder to encode a word before transmission over the input-output bus so that the difference in the number of 1 bits and the number of 0 bits in the encoded word is upper bounded, where the upper bound is less than the length of the original word before encoding. An embodiment circuit to implement this encoding comprises partitioning the word into a plurality of smaller words. An embodiment circuit further comprises a number of stages, where in the first stage, there are a plurality of encoders to encode in pair-wise fashion the smaller words. Additional stages also comprise a plurality of encoders, each encoder performing a pair-wise encoding of words outputted by a previous stage. Other embodiments are described and claimed.

Circuit to reduce rail noise voltage spikes due to switching on an input-output bus

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.

Minimizing transistor size in integrated circuits

A transistor structure is provided comprising a source region having a N source region and a N lightly doped source region. The structure also comprises a drain region having a N drain region and a N lightly doped drain region. A P heavily doped region is provided. The P region resides alongside at least a portion of at least one of the N lightly doped source region and N lightly doped drain region. A P body region resides below a gate of the device and between the source and drain regions. The P heavily doped region provides a capacitive coupling between a body region and the gate of the device and form a capacitive voltage divider with the junction capacitance of the device.

Capacitively coupled DTMOS on SOI

A lateral bipolar transistor includes a semiconductor layer overlying an electrically insulating material and an insulating layer overlying a central portion of the semiconductor layer. A contact hole resides in the insulating layer and a conductive material overlies the insulating layer and makes electrical contact with the semiconductor layer through the contact hole, thereby forming a base contact. The semiconductor layer has a first conductivity type in a central region which substantially underlies the conductive material, and has a second conductivity type in regions adjacent the central region. The first region forms a base region and the adjacent regions form a collector region and an emitter region, respectively. A method of forming a lateral bipolar transistor device is also disclosed. The method includes forming a semiconductor layer over an insulating material and forming an insulating layer over the semiconductor material. A base contact hole is then formed in the insulating layer and a conductive base contact region is formed over a portion of the insulating layer. The base contact region overlies the base contact hole and makes an electrical connection to a middle portion of the semiconductor layer, which corresponds to a base region. Lastly, a collector region and an emitter region are formed on opposite sides of the base region such that the collector region and the emitter region are adjacent the base region, respectively.

High-speed lateral bipolar device in SOI process

The memory cells at the very edge of an array are susceptible variations in transistor channel length and other attributes due to lithographic proximity effects. To reduce these undesirable edge effects, it is common to add non-functional sacrificial rows and columns of nearly identical memory cells around the periphery of a memory array. These &ldquo;guard&rdquo; cells (i.e., &ldquo;end&rdquo; cells, or &ldquo;edge&rdquo; cells) may provide, for at least the lower masking layers, a homogeneous lithographic environment at the edge of the functional array, but unfortunately consume area without adding to the storage capacity of the array. To save area, a group of functional memory cells in one array may also be used as guard cells for another memory array. The memory cells of the one array may, for example, be redundant memory cells serving the other memory array. In one embodiment having several memory submodules or banks, an array of four redundant rows is placed adjacent to the array of one of the memory banks. Separate sacrificial guard cells for the adjoining edge of the one memory bank are therefore no longer needed. Nonetheless, the lithographic environment at the edge of the regular array, for at least the lower masking layers, is homogeneous with the environment anywhere in the middle of the regular array. By abutting the redundant and normal memory cell arrays in this matter, the need for sacrificial guard cells for both arrays along their adjoining edges is eliminated, thus saving both layout area and layout complexity.

Use of functional memory cells as guard cells in a semiconductor memory

A coupling capacitor is coupled between the gate and the body region of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The body region of the MOSFET is electrically isolated to form a floating body region. The capacitance of the coupling capacitor is designed such that a BJT (Bipolar Junction Transistor) connected in parallel with the MOSFET turns on when the MOSFET turns on. In addition such a design of the coupling capacitor lowers the magnitude of the threshold voltage of the MOSFET when the MOSFET is turned on. Furthermore, the capacitance of the coupling capacitor is designed such that the magnitude of the threshold voltage of the MOSFET is raised when the MOSFET is turned off. Thus, the MOSFET type device of the present invention has both higher drive current when the MOSFET is turned on and lower steady state power dissipation when the MOSFET is turned off with a variable threshold voltage.

MOSFET-type device with higher driver current and lower steady state power dissipation

A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.

Forming minimal size spaces in integrated circuit conductive lines

A memory module configuration has been developed, which employs multi-level sensing, low-voltage-swing differential signal paths, and array layout techniques to better optimize area/speed/power tradeoffs. In some configurations two-level sensing is employed with secondary sense amplifiers positioned toward a middle of the memory module with memory banks or submodules positioned therearound. Primary sense-amplifiers in the submodules or banks sense differential signals on local bit-lines spanning the corresponding submodule or bank and drive a low-voltage-swing differential signal onto global bit-lines that span a subset of the submodules or banks. The global bit-lines are sensed by secondary sense amplifiers that drive data outputs across a subset of the submodules or banks toward output circuits. In some configurations the memory module is divided into upper and lower portions with upper global bit-lines spanning the upper portion and lower global bit-lines spanning the lower portion. Corresponding upper and lower global bit-lines are disjoint and are sensed by corresponding upper and lower secondary sense amplifiers. By this arrangement, the minimum to maximum variation in access time between the different rows of the memory module is reduced. Moreover, smaller drivers and lower power is achieved by use of such a two-level arrangement. In particular, area reductions and power reductions are achieved for submodule- or bank-resident primary sense amplifiers.

Layout for semiconductor memory including multi-level sensing

A temperature sensor is fabricated in an integrated circuit in combination with another device such as a microprocessor using a fabrication technology that is suitable for fabricating the device. Operation of the temperature sensor is based on the bandgap physics of semiconductors using a bandgap reference circuit and an amplifier that generate two measurement voltages, a voltage that is temperature-dependent and a voltage that is temperature-independent. The temperature sensor includes a bandgap power supply circuit that supplies a power supply voltage that is very stable to drive the temperature sensor so that the temperature sensor generates an output signal that is essentially independent of the power supply voltage.

Power supply independent temperature sensor

A redundancy configurations is described in which a redundant element is able to overpower a defective element without the need for physical disconnection or logical deselection and in which plural redundant rows (or columns) are provided to replace more than one defective row (or column) in an array or subarray. Redundancy configurations are further described in which a redundant element is able to overpower a defective element without the need for physical disconnection or logical deselection and in which a given redundant row (or column) may replace a defective row (or column) in one of plural subarrays representing distinct sets of rows (or columns).

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San Jose, CA, United States of America

John Christian Holst