The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2001
Filed:
Feb. 29, 2000
Applicant:
Inventors:
Craig S. Sander, Mountain View, CA (US);
Rich K. Klein, Mountain View, CA (US);
Asim A. Selcuk, Cupertino, CA (US);
Nicholas J. Kepler, San Jose, CA (US);
Christoper A. Spence, Sunnyvale, CA (US);
Raymond T. Lee, Sunnyvale, CA (US);
John C. Holst, San Jose, CA (US);
Stephen C. Horne, Austin, TX (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract
A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.