logo

For the Inventor, By the Inventor

Hsinchu, Taiwan

Jiunyu Tsai

This inventor holds 19 USPTO granted patents and 3 published patent applications, primarily in Magnetic Memory Technology. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jiunyu Tsai. Retrieved from https://idiyas.com/inventor/jiunyu-tsai

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 19 

% Patents Active = 94.7

Average Co-Inventor Count = 5.1

ph-index = 5

Forward Citations = 64(Granted Patents)


Location History:

  • Hsinchu City, TW (2018)
  • Hsinchu, TW (2017 - 2024)

Company Filing History:

goldMedal19 out of 42,965 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents

Years Active: 2017-2026

Loading Chart...
Areas of Expertise:
Magnetic Memory Device
MRAM Techniques
MTJ Top Electrode
Semiconductor Structure
Memory Cell
Via Interface
Manufacturing Method
Mixed-Dimension Structure
Void-Free Structure
Electrode Connection
Metal Layer Interface
Spacer Techniques
19 patents (USPTO):Explore Patents
1. 12563975 - Magnetic memory device and method for manufacturing the same (2026-02-24),
2. 12550619 - Techniques for MRAM MTJ top electrode connection (2026-02-10),
3. 12426514 - Techniques for MRAM MTJ top electrode connection (2025-09-23),
4. 12274183 - Memory cell with top electrode via (2025-04-08),
5. 12167614 - Techniques for MRAM MTJ top electrode to via interface (2024-12-10),
6. 11889769 - Memory cell with top electrode via (2024-01-30),
7. 11678493 - Semiconductor structure and manufacturing method of the same (2023-06-13),
8. 11489107 - Memory cell with top electrode via (2022-11-01),
9. 11469372 - Memory cell with top electrode via (2022-10-11),
10. 11189659 - Techniques for MRAM MTJ top electrode to via interface (2021-11-30),
11. 11075335 - Techniques for MRAM MTJ top electrode connection (2021-07-27),
12. 11043531 - Semiconductor structure and manufacturing method of the same (2021-06-22),
13. 11005032 - Techniques for MRAM MTJ top electrode to metal layer interface including spacer (2021-05-11),
14. 10797230 - Techniques for MRAM MTJ top electrode to metal layer interface including spacer (2020-10-06),
15. 10790439 - Memory cell with top electrode via (2020-09-29),

Title: Jiunyu Tsai: Innovator in Memory Technology

Introduction

Jiunyu Tsai is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of memory technology, holding a total of 17 patents. His work focuses on advanced techniques that enhance the performance and efficiency of memory devices.

Latest Patents

Among his latest patents are "Techniques for MRAM MTJ Top Electrode Connection" and "Memory Cell with Top Electrode Via." The first patent relates to an integrated chip featuring a memory cell that includes a top electrode and a top electrode via, designed to improve the connection and functionality of memory cells. The second patent describes an integrated chip that incorporates a memory device surrounded by a dielectric structure, which enhances data storage capabilities.

Career Highlights

Jiunyu Tsai is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His innovative work has positioned him as a key figure in the development of next-generation memory technologies.

Collaborations

He has collaborated with notable colleagues, including Hung Cho Wang and Sheng-Huang Huang, contributing to various projects that push the boundaries of memory technology.

Conclusion

Jiunyu Tsai's contributions to memory technology through his patents and collaborations highlight his role as an influential inventor in the semiconductor industry. His work continues to shape the future of memory devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…