The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 23, 2025

Filed:

Jul. 21, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Harry-Hak-Lay Chuang, Zhubei, TW;

Chen-Pin Hsu, Taoyuan, TW;

Hung Cho Wang, Taipei, TW;

Wen-Chun You, Dongshan Township, TW;

Sheng-Chang Chen, Hsinchu, TW;

Tsun Chung Tu, Tainan, TW;

Jiunyu Tsai, Hsinchu, TW;

Sheng-Huang Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); H01F 10/32 (2006.01); H01F 41/32 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); H01F 10/3259 (2013.01); H01F 41/32 (2013.01); H01L 21/76802 (2013.01); H01L 21/76819 (2013.01); H01L 21/7684 (2013.01); H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10B 61/22 (2023.02); H10N 50/80 (2023.02);
Abstract

Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.


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