The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 22, 2021

Filed:

Nov. 20, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Alexander Kalnitsky, San Francisco, CA (US);

Sheng-Huang Huang, Hsinchu, TW;

Harry-Hak-Lay Chuang, Hsinchu County, TW;

Jiunyu Tsai, Hsinchu, TW;

Hung Cho Wang, Taipei, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/00 (2006.01); H01L 27/22 (2006.01); H01L 43/02 (2006.01); H01F 10/32 (2006.01); H01F 41/34 (2006.01); G11C 11/16 (2006.01); H01L 43/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/226 (2013.01); G11C 11/161 (2013.01); H01F 10/3254 (2013.01); H01F 41/34 (2013.01); H01L 27/222 (2013.01); H01L 43/02 (2013.01); H01L 43/12 (2013.01); H01F 10/329 (2013.01);
Abstract

The present disclosure provides a semiconductor structure having a memory region. The semiconductor structure includes an Nmetal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the Nmetal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M)metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.


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