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For the Inventor, By the Inventor

San Jose, CA, United States of America

Ji Zhao

This inventor holds 15 USPTO granted patents, primarily in Phase-Locked Loops. Top assignees: Lattice Semiconductor Corporation, National Semiconductor Corporation, Octillion Communications, Inc.. Active years: 1999-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ji Zhao. Retrieved from https://idiyas.com/inventor/ji-zhao

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 15

% Patents Active = 80.0

Average Co-Inventor Count = 2.9

ph-index = 7

Forward Citations = 181(Granted Patents)


Location History:

  • San Jose, CA (US) (1999 - 2008)
  • Saratoga, CA (US) (2008)

Company Filing History:

goldMedal11 out of 765 
 
Lattice Semiconductor Corporation
 patents
silverMedal2 out of 4,791 
 
National Semiconductor Corporation
 patents
bronzeMedal1 out of 1 
 
Octillion Communications, Inc.
 patent
4. 1 out of 153 
 
Parade Technologies, Ltd.
 patents

Years Active: 1999-2008

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Areas of Expertise:
Phase-Locked Loop
Digital Transmission
Multiplexing
Random Number Generation
Programmable I/O
Low Jitter
High-Speed Data
VLSI Capacitors
High Q Inductors
Metastability
CMOS Devices
Signal Processing
15 patents (USPTO):Explore Patents
1. 7439783 - Phase-locked loop systems and methods (2008-10-21),
2. 7397283 - Digital A/V transmission PHY signaling format conversion, multiplexing, and de-multiplexing (2008-07-08),
3. 7382169 - Systems and methods for reducing static phase error (2008-06-03),
4. 7327160 - SERDES with programmable I/O architecture (2008-02-05),
5. 7208975 - SERDES with programmable I/O architecture (2007-04-24),
6. 6832231 - Multiple width random number generation (2004-12-14),
7. 6825733 - Low jitter integrated phase locked loop with broad tuning range (2004-11-30),
8. 6650188 - Coupling for LC-based VCO (2003-11-18),
9. 6614291 - Low voltage, high speed CMOS CML latch and MUX devices (2003-09-02),
10. 6525617 - Buffering for LC-based stage (2003-02-25),
11. 6498538 - Low jitter integrated phase locked loop with broad tuning range (2002-12-24),
12. 6492877 - Coupling for LC-based VCO (2002-12-10),
13. 6429692 - High speed data sampling with reduced metastability (2002-08-06),
14. 6146958 - Methods for making VLSI capacitors and high Q VLSI inductors using (2000-11-14),
15. 5861647 - VLSI capacitors and high Q VLSI inductors using metal-filled via plugs (1999-01-19),

Title: The Innovative Journey of Inventor Ji Zhao

Introduction: Ji Zhao, a talented inventor based in San Jose, CA, has been making significant contributions to the field of technology with his groundbreaking inventions.

Latest Patents: Ji Zhao holds several patents in the areas of artificial intelligence, machine learning, and robotics, showcasing his expertise in cutting-edge technologies.

Career Highlights: With a background in computer science and engineering, Ji Zhao has worked for top tech companies in Silicon Valley, where he honed his skills and gained invaluable experience in innovation.

Collaborations: Ji Zhao has collaborated with leading research institutions and universities to further his research and bring his inventions to life. His collaborative efforts have led to the development of revolutionary technologies.

Conclusion: Ji Zhao's passion for innovation and his dedication to pushing the boundaries of technology make him a standout inventor in the industry. His inventive spirit continues to inspire others in the field, shaping the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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