The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 05, 2008

Filed:

Feb. 16, 2007
Applicants:

OM P. Agrawal, Los Altos, CA (US);

Jock Tomlinson, Hillsboro, OR (US);

Kuang Chi, San Jose, CA (US);

Ji Zhao, San Jose, CA (US);

Ju Shen, San Jose, CA (US);

Jinghui Zhu, San Jose, CA (US);

Inventors:

Om P. Agrawal, Los Altos, CA (US);

Jock Tomlinson, Hillsboro, OR (US);

Kuang Chi, San Jose, CA (US);

Ji Zhao, San Jose, CA (US);

Ju Shen, San Jose, CA (US);

Jinghui Zhu, San Jose, CA (US);

Assignee:

Lattice Semiconductor Corporation, Hillsboro, OR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.


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