The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Jan. 20, 2005
OM P. Agrawal, Los Altos, CA (US);
Jock Tomlinson, Hillsboro, OR (US);
Kuang Chi, San Jose, CA (US);
Ji Zhao, San Jose, CA (US);
Ju Shen, San Jose, CA (US);
Jinghui Zhu, San Jose, CA (US);
Om P. Agrawal, Los Altos, CA (US);
Jock Tomlinson, Hillsboro, OR (US);
Kuang Chi, San Jose, CA (US);
Ji Zhao, San Jose, CA (US);
Ju Shen, San Jose, CA (US);
Jinghui Zhu, San Jose, CA (US);
Lattice Semiconductor Corporation, Hillsboro, OR (US);
Abstract
In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.