Lattice Semiconductor Corporation

National Semiconductor Corporation

Parade Technologies, Ltd.

Octillion Communications, Inc.

Ji Zhao

Ming Qu

Edwin Chan

Om P Agrawal

Ju Shen

Jinghui Zhu

Ludmil Nikolov

Kochung Lee

Chih Sieh Teng

Kuang Chi

Harald Weller

Jock F Tomlinson

Michael G France

Xueping Jiang

Jimmy Chiu

Improved common mode feedback techniques are provided for charge pumps, phase-locked loops (PLLs), and other circuits. For example, in accordance with an embodiment of the present invention, a circuit includes a loop filter having first and second loop filter nodes. An amplifier is provided having first and second differential inputs respectively coupled to the first and second loop filter nodes. A first current source is coupled to the first loop filter node and a second current source is coupled to the second loop filter node. The first and second current sources continuously adjust a common mode voltage of the loop filter nodes.

Phase-locked loop systems and methods

A circuit includes a configurable receiver circuit, a multiplexer or demultiplexer coupled to the configurable receiver circuit, and a configurable driver circuit coupled to the multiplexer or demultiplexer. The configurable receiver circuit generates an internal format signal which is received by the multiplexer or demultiplexer. The configurable driver circuit receives the internal format signal from the multiplexer or demultiplexer.

Digital A/V transmission PHY signaling format conversion, multiplexing, and de-multiplexing

In accordance with one or more embodiments of the present invention, a system includes a phase-locked loop circuit that receives a reference signal and a feedback signal and provides an output signal. A control circuit also receives the reference signal and the feedback signal and provides a correction current for the phase-locked loop circuit to reduce a phase error of the output signal.

Systems and methods for reducing static phase error

In one embodiment of the invention, a programmable integrated circuit includes a plurality of SERDES circuits; a plurality of input/output (I/O) circuits; and a routing structure configurable to provide one or more of the following connections over routing paths having deterministic routing delays: coupling a SERDES circuit to another SERDES circuit; coupling a SERDES circuit to an I/O circuit; coupling an I/O circuit to a SERDES circuit; and coupling an I/O circuit to another I/O circuit.

SERDES with programmable I/O architecture

In one embodiment, a programmable interconnect includes SERDES circuits dedicated to communicating high-speed data and input/output (I/O) circuits dedicated to communicating low-speed data. A routing structure is configurable to couple a SERDES circuit to another SERDES circuit, a SERDES circuit to an I/O circuit, an I/O circuit to a SERDES circuit, and an I/O circuit to another I/O circuit over routing paths having deterministic routing delays. In another embodiment, the routing structure includes a high-speed routing structure for communicating high-speed data to and from a SERDES circuit and a low-speed routing structure for communicating low-speed data to and from an I/O circuit.

Method and system for generating a multiple width (e.g., 16-bit width) pseudo-random number (PRN). Each of first and second 8-bit width PRNs is generated, using first and second LFSR configurations that incorporate first and second characteristic polynomials, at least one of which is irreducible. The first and second 8-bit PRNs are generated on a rising edge and on a falling edge, respectively, of a clock signal. The first and second 8-bit PRNs are combined by concatenation or by interleaving to form a 16-bit, or other multiple width, PRN.

Multiple width random number generation

System and method for providing a low noise signal having a broad tuning range (1 GHz to 10 GHz, or larger), with associated jitter no more than about 10 percent of the selected period of a target output signal. In a first stage, a ring-based VCO phase locked loop system provides a broad tuning range with some associated noise, and a second stage in a first state is relatively transparent, with no substantial differential attenuation based on frequency. After phase lock is achieved, the second stage is switched to a second state with low associated noise and high differential attenuation based on input signal frequency.

Low jitter integrated phase locked loop with broad tuning range

A two-stage coupling loop system that provides in-phase and quadrature signals in the two stages. Each stage includes a signal coupler, an LC-based voltage controlled oscillator (VCO) and an in-loop signal buffer that provides an additional controllable phase shift. Inclusion of the buffers in the loop decreases the capacitance load of each VCO.

Coupling for LC-based VCO

A signal multiplexer system and a signal latch system for low voltage (V &ap;1.2 volts) and high speed transitions between states. A dc signal isolation circuit, inserted between a clock signal circuit and a signal input/output circuit, allows use of a two-transistor-layer vertical structure that provides adequate headroom voltage (about 0.3-0.4 volts, or larger) for high speed transistor response.

Low voltage, high speed CMOS CML latch and MUX devices

A two-stage ring oscillator system that provides a phase shift of 90&deg; in each of the two stages. Each stage includes an LC-based stage including a voltage controlled oscillator (VCO) and an in-line signal buffer that provides an additional controllable phase shift in the forward path and reduces loading capacitance of each LC-based stage by an estimated 10-50 percent. In-phase and quadrature output signals are provided by the system.

Buffering for LC-based stage

System and method for providing low noise signal having a broad tuning range (1 GHz to 10 GHz, or larger), with associated jitter no more than about 10 percent of the selected period of a target output signal. In a first stage, a ring-based VCO phase locked loop system provides a broad tuning range with some associated noise, and a second stage in a first state is relatively transparent, with no substantial differential attenuation based on frequency. After phase lock is achieved, the second stage is switched to a second state with low associated noise and high differential attenuation based on input signal frequency.

A two-stage coupling loop system that provides in-phase and quadrature signals in two stages. Each stage includes a signal coupler, an LC-based voltage controlled oscillator (VCO) and in-loop signal buffer that provides an additional controllable phase shift. Inclusion of the buffers in the loop decreases the capacitance load of each VCO.

A data sampling system, including a data tracking circuit and a data latching circuit, that reduces the likelihood of metastability that arises through competition of the two circuits, where data sampling occurs in a transition time interval. A combined latching and weakened tracking circuit is provided in which the tracking operation cannot change an output signal from the latching operation after the latch resolves a valid logical state.

High speed data sampling with reduced metastability

Disclosed are methods of making inductors and capacitors, comprising filling a via in a dielectric disposed between two metal layers with a metal plug. The plug comprises tungsten, aluminum or copper and extends the length of the metal layers. The plug connects the two metal layers to form the inductor. Two plugs can be formed so as to connect the two metal layers so as to form a parallel plate capacitor.

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San Jose, CA, United States of America

Ji Zhao