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For the Inventor, By the Inventor

Kaohsiung, Taiwan

Ji-Jan Chen

This inventor holds 17 USPTO granted patents, primarily in Integrated Circuit Design. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Industrial Technology Research Institute, National Central University. Active years: 2011-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ji-Jan Chen. Retrieved from https://idiyas.com/inventor/ji-jan-chen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 17

% Patents Active = 64.7

Average Co-Inventor Count = 4.7

ph-index = 3

Forward Citations = 45(Granted Patents)


Location History:

  • Hsin-Chu, TW (2012 - 2014)
  • Kaosiung, TW (2017)
  • Kaohsiung, TW (2011 - 2022)

Company Filing History:

goldMedal14 out of 43,553 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal3 out of 9,318 
 
Industrial Technology Research Institute
 patents
bronzeMedal1 out of 425 
 
National Central University
 patents
where one patent can have more than one assignee

Years Active: 2011-2022

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Areas of Expertise:
Phase-Locked Loop
Integrated Circuits
Defect Diagnosis
Yield Evaluation
Robustness Verification
Micro-Bump-Probe Pad
Clock Skew Compensation
Dynamic IR Voltage Drop
Built-In Self-Test
Floorplanning
Routing Co-Design
Jitter Measurement
17 patents (USPTO):Explore Patents
1. 11411571 - Phase-locked loop monitor circuit (2022-08-09),
2. 11025261 - Phase-locked loop monitor circuit (2021-06-01),
3. 10680627 - Phase-locked loop monitor circuit (2020-06-09),
4. 10256828 - Phase-locked loop monitor circuit (2019-04-09),
5. 10156609 - Device and method for robustness verification (2018-12-18),
6. 9847318 - Monolithic stacked integrated circuits with a redundant layer for repairing defects (2017-12-19),
7. 9766286 - Defect diagnosis (2017-09-19),
8. 9310431 - Diagnosis framework to shorten yield learning cycles of advanced processes (2016-04-12),
9. 9269640 - Repairing monolithic stacked integrated circuits with a redundant layer and lithography process (2016-02-23),
10. 8863062 - Methods and apparatus for floorplanning and routing co-design (2014-10-14),
11. 8832511 - Built-in self-test for interposer (2014-09-09),
12. 8707238 - Method to determine optimal micro-bump-probe pad pairing for efficient PGD testing in interposer designs (2014-04-22),
13. 8614571 - Apparatus and method for on-chip sampling of dynamic IR voltage drop (2013-12-24),
14. 8384455 - Apparatus for clock skew compensation (2013-02-26),
15. 8144756 - Jitter measuring system and method (2012-03-27),

Title: Innovations by Ji-Jan Chen: A Leader in Phase-Locked Loop Technologies

Introduction

Ji-Jan Chen, an accomplished inventor located in Kaohsiung, Taiwan, has made significant contributions to the field of electronics, particularly in the development of phase-locked loop circuits. With an impressive portfolio of 17 patents, his innovative work continues to shape the technological landscape.

Latest Patents

Among his latest innovations is a phase-locked loop monitor circuit designed for clock distribution. This innovative clock distribution circuit is configured to output a clock signal and includes a unique first circuit that utilizes a reference clock signal to generate both first and second reference signals. The second reference signal plays a crucial role by indicating whether the first reference signal is locked with the reference clock signal. The circuit also incorporates a second element designed to use the reference clock signal to produce an output signal, along with an indication signal that signifies whether the output signal is synchronized with the reference clock. Additionally, a monitor circuit links the first and second circuits, using signals from the first set to ascertain the proper functioning of the second circuit.

Career Highlights

Ji-Jan Chen has garnered experience from his work with renowned companies, including Taiwan Semiconductor Manufacturing Company Ltd. and the Industrial Technology Research Institute. His time spent in these organizations has enabled him to refine his skills and further his innovative pursuits.

Collaborations

Throughout his career, Ji-Jan has collaborated with talented individuals such as Yun-Han Lee and Sandeep Kumar Goel. These partnerships have contributed to the advancement of his projects and the successful implementation of his inventions.

Conclusion

With a remarkable track record of patents and pivotal contributions to electronics, Ji-Jan Chen stands as a prominent figure in the field of phase-locked loop technologies. His latest inventions not only reflect his expertise but also promise to lead to more groundbreaking advancements in the future.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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