Kaohsiung, Taiwan

I-Hsieh Wong

This inventor holds 33 USPTO granted patents and 14 published patent applications, primarily in Semiconductor Devices. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., National Taiwan University. Active years: 2017-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: I-Hsieh Wong. Retrieved from https://idiyas.com/inventor/i-hsieh-wong

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33 

% Patents Active = 100.0

Average Co-Inventor Count = 4.6

ph-index = 4

Forward Citations = 32(Granted Patents)


Location History:

  • Kaohsiung, TW (2017 - 2023)
  • Hsinchu, TW (2021 - 2024)

Company Filing History:


Years Active: 2017-2026

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Areas of Expertise:
Semiconductor Device
FinFET
Nano-FET
Epitaxial Layer
Dielectric Structures
Multi-Gate Transistors
Stressor Layer
Parasitic Capacitance
Field Effect Transistor
Hybrid SRAM Design
Source/Drain Features
Contact Plug
33 patents (USPTO):Explore Patents

Title: The Innovations of I-Hsieh Wong: A Leader in Semiconductor Technology

Introduction: I-Hsieh Wong, based in Kaohsiung, Taiwan, is a prolific inventor with a remarkable portfolio of 24 patents. His contributions to the field of semiconductor technology have significantly advanced the methods and devices used in the industry. Wong's work showcases not only his technical expertise but also his innovative mindset in tackling complex challenges within the semiconductor sector.

Latest Patents: Among his latest patents, Wong's work on "Methods for forming source/drain features" presents a sophisticated approach to semiconductor structures. This patent outlines a method that includes a series of intricate processes, from forming a trench in the source/drain region to creating an epitaxial source/drain feature encapsulated by fin sidewall spacers. Another notable patent, "Nano-FET semiconductor device and method of forming," utilizes a unique two-layer inner spacer structure designed to enhance the mechanical properties of nano-FET devices. These innovations are a testament to Wong’s ability to blend scientific principles with practical applications, pushing the boundaries of current technology.

Career Highlights: I-Hsieh Wong has made significant strides in his career, having worked with leading institutions including Taiwan Semiconductor Manufacturing Company Limited and National Taiwan University. His experience in these renowned organizations has provided him with the platform to develop groundbreaking technologies that influence the semiconductor landscape.

Collaborations: Throughout his career, Wong has collaborated with esteemed colleagues such as Wei-Yang Lee and Samuel C. Pan. These partnerships have fostered an environment of shared knowledge and creativity, resulting in advancements that benefit the broader field of semiconductor research.

Conclusion: I-Hsieh Wong's dedication to innovation is evident through his extensive patent portfolio and impactful collaborations. His contributions to semiconductor technology not only reflect his expertise but also his commitment to advancing the industry. As he continues to develop new technologies, the impact of his work will surely resonate throughout the field for years to come.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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