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For the Inventor, By the Inventor

San Jose, CA, United States of America

Huahung Kao

This inventor holds 29 USPTO granted patents and 4 published patent applications and 2 EPO patents, primarily in Semiconductor Packaging. Top assignees: Marvell International Limited, Marvellworld Trade Ltd., Marvell Asia Pte., Ltd.. Active years: 2009-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Huahung Kao. Retrieved from https://idiyas.com/inventor/huahung-kao

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29 

% Patents Active = 69.0

 

Average Co-Inventor Count = 2.3

ph-index = 5

Forward Citations = 131(Granted Patents)


Company Filing History:

goldMedal16 out of 5,162 
 
Marvell International Limited
 patents
silverMedal10 out of 1,901 
 
Marvellworld Trade Ltd.
 patents
bronzeMedal3 out of 1,234 
 
Marvell Asia Pte., Ltd.
 patents

Years Active: 2009-2025

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Areas of Expertise:
Integrated Circuit
Stack Die Structure
Heat Sink Design
Flip Chip
Package-on-Package
Decoupling Capacitor
Leadframe
Electronic Assembly
Multi-Chip Module
BGA Substrate
Conductive Bumps
Interconnect Layouts
29 patents (USPTO):Explore Patents
1. 12199003 - Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure (2025-01-14),
2. 11469295 - Decoupling capacitor integrated in system on chip (SOC) device (2022-10-11),
3. 11282762 - Heat sink design for flip chip ball grid array (2022-03-22),
4. 10128171 - Leadframe with improved half-etch layout to reduce defects caused during singulation (2018-11-13),
5. 9666571 - Package-on-package structures (2017-05-30),
6. 9543236 - Pad configurations for an electronic package assembly (2017-01-10),
7. 9524927 - Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types (2016-12-20),
8. 9355951 - Interconnect layouts for electronic assemblies (2016-05-31),
9. 9331052 - Pad configurations for an electronic package assembly (2016-05-03),
10. 9209163 - Package-on-package structures (2015-12-08),
11. 9123699 - Formation of package pins in semiconductor packaging (2015-09-01),
12. 8963342 - Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types (2015-02-24),
13. 8940585 - Single layer BGA substrate process (2015-01-27),
14. 8912664 - Leadless multi-chip module structure (2014-12-16),
15. 8860193 - Pad configurations for an electronic package assembly (2014-10-14),

Title: The Innovative Journey of Huahung Kao

Introduction:

Huahung Kao, a visionary inventor based in San Jose, CA, has made significant contributions to the field of technology through his groundbreaking innovations.

Latest Patents:

Huahung Kao's latest patents include cutting-edge advancements in artificial intelligence algorithms for autonomous vehicles, revolutionizing the way we approach transportation technology.

Career Highlights:

With a career spanning over two decades, Huahung Kao has worked with leading tech companies in Silicon Valley, spearheading research and development projects that have pushed the boundaries of innovation.

Collaborations:

Throughout his career, Huahung Kao has collaborated with top researchers and engineers from renowned universities and research institutions, fostering a culture of creativity and excellence in technological advancement.

Conclusion:

In conclusion, Huahung Kao's relentless pursuit of innovation and his passion for pushing the limits of technology have solidified his position as a trailblazing inventor in the ever-evolving landscape of the tech industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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