Marvell International Limited

Marvellworld Trade Ltd.

Marvell Asia Pte., Ltd.

Huahung Kao

Shiann-Ming Liou

Tyson Leistiko

Albert M Wu

Sehat Sutardja

Wayne A Loeb

Chenglin Liu

Runzi Chang

Richard Stephen Graf

Thomas T Ngo

Luke England

Ronen Sinai

An electronic device disposed in a package that includes: an interposer, fan-out interconnect (FOI), and a lid. The interposer having first size and first surface upon which die terminals (DTs) are disposed and are configured to electrically couple to integrated circuit die (IC), and second surface upon which substrate terminals (STs) are disposed and are configured to electrically couple to substrate. The IC has second size smaller than the first size, and the IC is mounted on the first surface in electrical contact with the DTs, the interposer is mounted on third surface, and the package substrate has third size, larger than the first size. The FOI establishes electrical interconnection between DTs and STs, the DTs have first pitch size and the STs have second pitch size, larger than first pitch size. The lid has first section, configured to abut fourth surface, and second section, mounted on the third surface.

Packaging stacked substrates and an integrated circuit die using a lid and a stiffening structure

A system on a chip (SOC) device includes a substrate, processing circuitry formed on the substrate, and noise reduction circuitry formed on the processing circuitry. The noise reduction circuitry is configured to reduce noise caused by variations in current consumed by the processing circuitry. The noise reduction circuitry includes a decoupling capacitor, which includes (i) two or more first layers, (ii) one or more second layers interleaved between the first layers, (iii) dielectric layers formed between adjacent first and second layers and configured to electrically isolate between the adjacent first and second layers, (iv) a first contact, which is electrically connected to the first layers so as to form a first electrode of the decoupling capacitor, and (v) a second contact, which is electrically connected to the second layers so as to form a second electrode of the decoupling capacitor.

Decoupling capacitor integrated in system on chip (SOC) device

A flip chip ball grid array (FCBGA) comprises a substrate, a cavity forming ring stiffener, an external heat sink, and a thermal interface material. The cavity forming ring stiffener is disposed on the substrate. The cavity forming ring stiffener has a segment which forms a cavity with the substrate, and exposes a top of the silicon chip. The external heat sink is disposed on the silicon chip and the segment of the cavity forming ring stiffener. A thermal interface material separates the segment of the cavity forming ring stiffener and the top of the silicon chip from the external heat sink and conducts heat from the silicon chip to the external heat sink.

Heat sink design for flip chip ball grid array

A leadframe matrix for mounting and packaging semiconductor dice includes a plurality of leadframes each including leads arranged along peripheral sides thereof. An interconnecting leadframe portion connects a first peripheral side of a first one of the plurality of leadframes to a second peripheral side of a second one of the plurality of leadframes. The leads along the first peripheral side include partially etched portions. The partially etched portions of the leads are at least partially contiguous with and connected to the interconnecting leadframe portions.

Leadframe with improved half-etch layout to reduce defects caused during singulation

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Package-on-package structures

Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

Pad configurations for an electronic package assembly

Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting a packaging type for an integrated circuit. A structure generally includes a bump pad having a plurality of electrically disconnected bump pad sections, a plurality of bond pads each configured for electrical connection to one of the bump pad sections, and a plurality of conductive traces, each adapted to electrically connect one of the bond pads to the one bump pad section. A method generally includes the steps of forming the bump pad, the bond pads, and the conductive traces from an uppermost metal layer, and forming an insulation layer thereover. Another method generally includes forming the uppermost metal layer, and forming either a wire bond to at least one of the bond pads, or a ball bond or solder ball to electrically connect the bump pad section.

Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types

Embodiments of the present disclosure provide an apparatus including an electronic device and a substrate to receive the electronic device, the electronic device being electrically coupled to the substrate using a plurality of interconnect structures, the interconnect structures being arranged on the electronic device based at least in part on a layout of the substrate. Other embodiments may be described and/or claimed.

Interconnect layouts for electronic assemblies

Embodiments provide a method of fabricating a semiconductor package, the method comprising forming a leadframe, wherein the leadframe includes an inner lead, and wherein a bottom surface of the inner lead comprises a first section and a second section; depositing an oxidation resistant material on the first section of the bottom surface of the inner lead; and forming an oxidation layer on the second section of the bottom surface of the inner lead, wherein the oxidation resistant material deposited on the first section of the bottom surface of the inner lead prevents the oxidation layer from forming on the first section of the bottom surface of the inner lead.

Formation of package pins in semiconductor packaging

Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting one of a plurality of packaging types for an integrated circuit. The structure generally comprises a bump pad, a plurality of bond pads configured for independent electrical connection to the bump pad, and a plurality of conductive traces, each adapted to electrically connect one of the bond pads to the bump pad. The method of configuring generally includes the steps of forming the bump pad, the bond pads, and the conductive traces from an uppermost metal layer, and forming an insulation layer thereover. The method of selecting generally comprises the uppermost metal layer-forming step, and forming either (i) a wire bond to at least one of the bond pads, or (ii) a bumping metal configured to electrically connect at least one of the bond pads to the bump pad.

The present disclosure provides semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material.

Single layer BGA substrate process

Multi-chip quad flat no-lead (QFN) packages and methods for making the same are disclosed. A multi-chip package may include a first die including a plurality of first bond pads, wherein selected first bond pads are wire-bonded to a first side of a leadframe, and a second die mounted on the first die and including a plurality of second bond pads, wherein selected second bond pads are wire-bonded to a second side, opposite the first side, of the leadframe. Another package may include a first die including a plurality of first bond pads, wherein selected first bond pads are wire-bonded to a first side of a leadframe, and a second die flip-chip mounted on a second side of the leadframe and including a plurality of second bond pads, wherein selected second bond pads are bonded to the second side of the leadframe. Other embodiments are also described.

Leadless multi-chip module structure

Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. Other embodiments may be described and/or claimed.

Growing community of inventors

San Jose, CA, United States of America

Huahung Kao