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For the Inventor, By the Inventor

Tokyo, Japan

Hisayuki Nagamine

This inventor holds 25 USPTO granted patents and 8 published patent applications, primarily in Semiconductor Devices. Top assignees: Ps4 Luxco S.a.r.l., Elpida Memory, Inc., Micron Technology Incorporated. Active years: 1994-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hisayuki Nagamine. Retrieved from https://idiyas.com/inventor/hisayuki-nagamine

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25 

% Patents Active = 64.0

Average Co-Inventor Count = 1.8

ph-index = 5

Forward Citations = 61(Granted Patents)


Company Filing History:

goldMedal9 out of 377 
 
Ps4 Luxco S.a.r.l.
 patents
silverMedal7 out of 1,458 
 
Elpida Memory, Inc.
 patents
bronzeMedal2 out of 39,176 
 
Micron Technology Incorporated
 patents
4. 2 out of 36,676 
 
Nec Corporation
 patents
5. 1 out of 190 
 
Powerchip Semiconductor Manufacturing Corporation
 patents
6. 4 out of 834,453 
Other
 patents

Years Active: 1994-2023

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Areas of Expertise:
Amplifier Layout
Power Supply Stabilization
Mesh-Pattern Wirings
Data Buses
Compensation Capacitor
Thermal Management
Wiring Layers
Integrated Circuit
Memory Device
Circuit Configuration
Parasitic Parameters
25 patents (USPTO):Explore Patents
1. 11581033 - Sub-sense amplifier layout scheme to reduce area (2023-02-14),
2. 10128802 - Semiconductor device including amplifier (2018-11-13),
3. 9742361 - Semiconductor device including amplifier (2017-08-22),
4. 9478525 - Semiconductor device (2016-10-25),
5. 9337139 - Semiconductor device having compensation capacitor to stabilize power supply voltage (2016-05-10),
6. 9059165 - Semiconductor device having mesh-pattern wirings (2015-06-16),
7. 8928109 - Semiconductor device (2015-01-06),
8. 8860187 - Semiconductor device (2014-10-14),
9. 8860094 - Semiconductor device with power supply line system of reduced resistance (2014-10-14),
10. 8848460 - Semiconductor device having plural data buses and plural buffer circuits connected to data buses (2014-09-30),
11. 8830773 - Semiconductor device having compensation capacitance (2014-09-09),
12. 8823173 - Semiconductor device having plurality of wiring layers and designing method thereof (2014-09-02),
13. 8767484 - Semiconductor device (2014-07-01),
14. 8717795 - Semiconductor device having plural circuit blocks operating at the same timing (2014-05-06),
15. 8704339 - Semiconductor device (2014-04-22),

Title: The Inventor Spotlight: Hisayuki Nagamine

Introduction:

Hisayuki Nagamine, a prolific inventor based in Tokyo, JP, has made significant contributions to the field of semiconductor technology. With an impressive portfolio of 25 patents, Nagamine continues to push the boundaries of innovation in the industry.

Latest Patents:

His latest patents showcase his expertise in the design of semiconductor devices. One notable invention is the "Sub-sense amplifier layout scheme to reduce area" which optimizes the layout of a sub-sense amplifier to enhance efficiency and functionality. Additionally, Nagamine's "Semiconductor device including amplifier" patent highlights his ingenuity in developing advanced electronic components.

Career Highlights:

Throughout his career, Nagamine has worked with leading companies such as Ps4 Luxco S.a.r.l. and Elpida Memory, Inc. His tenure at these renowned organizations has provided him with invaluable experience and insights into the dynamic world of semiconductor technology.

Collaborations:

Nagamine has had the privilege of collaborating with esteemed professionals in the industry, including Koji Yasumori and Tomohiro Kitano. Together, they have worked on cutting-edge projects that have pushed the boundaries of innovation and set new standards in the field.

Conclusion:

In conclusion, Hisayuki Nagamine stands as a pioneering figure in the realm of semiconductor innovation. His relentless pursuit of excellence and track record of success underscore his status as a visionary inventor shaping the future of technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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