The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 25, 2016

Filed:

Jun. 12, 2014
Applicant:

Ps4 Luxco S.a.r.l., Luxembourg, LU;

Inventors:

Machio Segawa, Tokyo, JP;

Hisayuki Nagamine, Tokyo, JP;

Assignee:

PS4 LUXCO S.A.R.L., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01); H01L 25/18 (2006.01); H01L 21/66 (2006.01); H01L 23/60 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 23/481 (2013.01); H01L 23/522 (2013.01); H01L 23/5286 (2013.01); H01L 24/17 (2013.01); H01L 27/092 (2013.01); H01L 22/32 (2013.01); H01L 23/60 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/18 (2013.01); H01L 27/0248 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05568 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/81193 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01);
Abstract

One semiconductor device includes nine surface micro-bumps laid out in a 3×3 matrix on a semiconductor substrate, a transistor that contains first and second diffusion layers formed on the semiconductor substrate, and power-supply wiring laid out on the semiconductor substrate. The aforementioned first diffusion layer is connected to one of the surface micro-bumps, the second diffusion layer is connected to the power-supply wiring, and the transistor is laid out in the region between the surface micro-bumps located on one edge in an X direction and the surface micro-bumps located on the other edge in said X direction.


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