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For the Inventor, By the Inventor

Plano, TX, United States of America

Hiroshi Yasuda

This inventor holds 13 USPTO granted patents and 5 published patent applications. Top assignees: Texas Instruments Corporation, Texas Instruments Incorporated Deutschland, Gmbh. Active years: 2009-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroshi Yasuda. Retrieved from https://idiyas.com/inventor/hiroshi-yasuda-7j81530z

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 13 

% Patents Active = 100.0

Average Co-Inventor Count = 2.6

ph-index = 2

Forward Citations = 15(Granted Patents)


Location History:

  • Dallas, TX (US) (2009)
  • Munich, DE (2010)
  • Plano, TX (US) (2010 - 2024)

Company Filing History:

goldMedal12 out of 29,922 
 
Texas Instruments Corporation
 patents
silverMedal2 out of 371 
 
Texas Instruments Incorporated Deutschland, Gmbh
 patents
where one patent can have more than one assignee

Years Active: 2009-2024

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13 patents (USPTO):Explore Patents
1. 12068402 - Dopant profile control in heterojunction bipolar transistor (HBT) (2024-08-20),
2. 11923442 - Bipolar transistor with segmented emitter contacts (2024-03-05),
3. 10026815 - Ultrashallow emitter formation using ALD and high temperature short time annealing (2018-07-17),
4. 8847359 - High voltage bipolar transistor and method of fabrication (2014-09-30),
5. 8828835 - Ultrashallow emitter formation using ALD and high temperature short time annealing (2014-09-09),
6. 8754484 - Bipolar transistor in bipolar-CMOS technology (2014-06-17),
7. 8536002 - Bipolar transistor in bipolar-CMOS technology (2013-09-17),
8. 8450179 - Semiconductor device having a first bipolar device and a second bipolar device and method for fabrication (2013-05-28),
9. 8294218 - Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection (2012-10-23),
10. 8012842 - Method for fabricating isolated integrated semiconductor structures (2011-09-06),
11. 7772057 - Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection (2010-08-10),
12. 7670890 - Silicide block isolated junction field effect transistor source, drain and gate (2010-03-02),
13. 7615425 - Open source/drain junction field effect transistor (2009-11-10),

Title: Hiroshi Yasuda: Innovator in Semiconductor Technology

Introduction

Hiroshi Yasuda is a prominent inventor based in Plano, TX, known for his significant contributions to semiconductor technology. With a total of 13 patents to his name, Yasuda has made remarkable advancements in the field, particularly in the design and functionality of heterojunction bipolar transistors.

Latest Patents

Yasuda's latest patents include innovative designs that enhance the performance of semiconductor devices. One notable patent focuses on dopant profile control in heterojunction bipolar transistors (HBT). This invention describes a semiconductor device structure that includes a collector region, a base region, and an emitter region, with a specific concentration gradient of the dopant that optimizes device performance. Another significant patent involves a bipolar transistor with segmented emitter contacts, which details an integrated circuit design that achieves a common-emitter current gain greater than 3500, showcasing Yasuda's expertise in enhancing transistor efficiency.

Career Highlights

Throughout his career, Hiroshi Yasuda has worked with leading companies in the semiconductor industry, including Texas Instruments Corporation and Texas Instruments Incorporated Deutschland, GmbH. His work at these organizations has allowed him to develop cutting-edge technologies that have had a lasting impact on the industry.

Collaborations

Yasuda has collaborated with notable professionals in the field, including Badih El-Kareh and Scott Balster. These partnerships

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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