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For the Inventor, By the Inventor

Yokkaichi, Japan

Hiroshi Nakatsuji

This inventor holds 10 USPTO granted patents and 5 published patent applications. Top assignee: Sandisk Technologies Inc.. Active years: 2019-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroshi Nakatsuji. Retrieved from https://idiyas.com/inventor/hiroshi-nakatsuji

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 10 

% Patents Active = 100.0

Average Co-Inventor Count = 3.7

ph-index = 3

Forward Citations = 63(Granted Patents)


Company Filing History:

goldMedal10 out of 4,955 
 
Sandisk Technologies Inc.
 patents

Years Active: 2019-2024

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10 patents (USPTO):Explore Patents
1. 12094944 - Transistor circuits including fringeless transistors and method of making the same (2024-09-17),
2. 11837640 - Transistors with stepped contact via structures and methods of forming the same (2023-12-05),
3. 11837601 - Transistor circuits including fringeless transistors and method of making the same (2023-12-05),
4. 11626496 - High voltage field effect transistors with self-aligned silicide contacts and methods for making the same (2023-04-11),
5. 11575015 - High voltage field effect transistors with self-aligned silicide contacts and methods for making the same (2023-02-07),
6. 11088152 - Static random access memory cell employing n-doped PFET gate electrodes and methods of manufacturing the same (2021-08-10),
7. 10770459 - CMOS devices containing asymmetric contact via structures (2020-09-08),
8. 10714486 - Static random access memory cell employing n-doped PFET gate electrodes and methods of manufacturing the same (2020-07-14),
9. 10355017 - CMOS devices containing asymmetric contact via structures and method of making the same (2019-07-16),
10. 10290645 - Three-dimensional memory device containing hydrogen diffusion barrier layer for CMOS under array architecture and method of making thereof (2019-05-14),

Title: Innovations of Hiroshi Nakatsuji

Introduction

Hiroshi Nakatsuji is a prominent inventor based in Yokkaichi, Japan. He has made significant contributions to the field of transistor technology, holding a total of 10 patents. His work focuses on enhancing the performance and efficiency of field effect transistors.

Latest Patents

One of his latest patents involves transistor circuits that include fringeless transistors and methods of making the same. This innovation features a field effect transistor that comprises a gate dielectric and a gate electrode overlying an active region, which contacts a sidewall of a trench isolation structure. The design allows for a fringeless transistor where the gate electrode does not overlie a portion of the trench isolation region. Additionally, a planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure is designed with a z-shaped vertical cross-sectional profile to ensure contact with the gate electrode while providing a segment that overlies the planar dielectric spacer plate. Furthermore, a conductive gate connection structure may be included to establish electrical connections between two electrodes of adjacent field effect transistors.

Career Highlights

Hiroshi Nakatsuji has built a successful career at Sandisk Technologies Inc., where he continues to innovate in the field of semiconductor technology. His expertise in transistor design has positioned him as a key figure in advancing electronic components.

Collaborations

Throughout his career, Nakatsuji has collaborated with notable colleagues, including Hiroyuki Ogawa and Dai Iwata. These partnerships have fostered a creative environment that has led to groundbreaking advancements in their field.

Conclusion

Hiroshi Nakatsuji's contributions to transistor technology exemplify the spirit of innovation. His patents and collaborations reflect a commitment to advancing electronic components, making a lasting impact in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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