Sandisk Technologies Inc.

Hiroshi Nakatsuji

Hiroyuki Ogawa

Kazutaka Yoshizawa

Dai Iwata

Jun Akaiwa

Akira Inoue

Kiyokazu Shishido

Mitsuhiro Togo

Shigeki Shimomura

Eiichi Fujikura

Yasuyuki Aoki

Masashi Ishida

Yasushi Ishii

A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.

Transistor circuits including fringeless transistors and method of making the same

A transistor includes a semiconductor substrate including a first active region, a second active region, and a semiconductor channel, a gate stack structure that overlies the semiconductor channel, a proximal dielectric material layer overlying the semiconductor substrate, laterally surrounding the gate stack structure, a distal dielectric material layer overlying the proximal dielectric material layer, and a first contact via structure contacting the first active region having a greater lateral extent at a level of the proximal dielectric material layer than at a level of the distal dielectric material layer.

Transistors with stepped contact via structures and methods of forming the same

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

High voltage field effect transistors with self-aligned silicide contacts and methods for making the same

Field effect transistors for an SRAM cell can be formed employing n-doped gate electrode portions for p-type pull-up transistors. The SRAM cell includes a first series connection of a first p-type pull-up transistor and a first n-type pull-down transistor located between a power supply source and electrical ground, and a second series connection of a second p-type pull-up transistor and a second n-type pull-down transistor located between the power supply source and the electrical ground. Each gate electrode of the SRAM cell can include a respective n-doped gate electrode portion.

Static random access memory cell employing n-doped PFET gate electrodes and methods of manufacturing the same

A silicon oxide liner, a silicon nitride liner, and a planarization silicon oxide layer may be sequentially formed over p-type and n-type field effect transistors. A patterned dielectric material layer covers an entirety of the n-type field effect transistor and does not cover at least a fraction of each area of p-doped active regions. An anisotropic etch process is performed to form p-type active region via cavities extending to a respective top surface of the p-doped active regions and n-type active region via cavities having a respective bottom surface at, or within, one of the silicon nitride liner and the silicon oxide liner. Boron-doped epitaxial pillar structures may be formed on top surfaces of the p-type active regions employing a selective epitaxy process. The n-type active region via cavities are extended to top surfaces of the n-doped active regions. Contact via structures are formed in the via cavities.

CMOS devices containing asymmetric contact via structures

A CMOS device includes a p-type field effect transistor containing p-doped active regions, an n-type field effect transistor containing n-doped active regions, a silicon oxide layer overlying the n-type field effect transistor and not overlying the p-type field effect transistor, boron-doped epitaxial pillar structures contacting a top surface of, and epitaxially aligned to, a respective one of the p-doped active regions, first active region contact via structures contacting a top surface of a respective one of the boron-doped epitaxial pillar structures, and second active region contact via structures contacting a top surface of a respective one of the n-doped active regions.

CMOS devices containing asymmetric contact via structures and method of making the same

A semiconductor structure includes a semiconductor device, a hydrogen diffusion barrier layer, a lower metal line structure located below the hydrogen diffusion barrier layer, an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack in a memory array region, a through-stack contact via structure extending through the alternating stack and through the hydrogen diffusion barrier layer in the memory array region and contacting the lower metal line structure, and a through-stack insulating spacer laterally surrounding the through-stack contact via structure and extending through the alternating stack but not extending through the hydrogen diffusion barrier layer.

Growing community of inventors

Yokkaichi, Japan

Hiroshi Nakatsuji