The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2023

Filed:

May. 10, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Jun Akaiwa, Yokkaichi, JP;

Dai Iwata, Yokkaichi, JP;

Hiroshi Nakatsuji, Yokkaichi, JP;

Eiichi Fujikura, Yokkaichi, JP;

Hiroyuki Ogawa, Nagoya, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); H01L 27/06 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
H01L 27/088 (2013.01); H01L 21/82385 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 23/5226 (2013.01); H01L 27/0629 (2013.01); H01L 27/0928 (2013.01);
Abstract

A field effect transistor includes a gate dielectric and a gate electrode overlying an active region and contacting a sidewall of a trench isolation structure. The transistor may be a fringeless transistor in which the gate electrode does not overlie a portion of the trench isolation region. A planar dielectric spacer plate and a conductive gate cap structure may overlie the gate electrode. The conductive gate cap structure may have a z-shaped vertical cross-sectional profile to contact the gate electrode and to provide a segment overlying the planar dielectric spacer plate. Alternatively or additionally, a conductive gate connection structure may be provided to provide electrical connection between two electrodes of adjacent field effect transistors.


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