IDiyas

For the Inventor, By the Inventor

Hyogo, Japan

Hirokazu Yonezawa

USPTO Granted Patents = 12

Average Co-Inventor Count = 1.6

ph-index = 8

Forward Citations = 180(Granted Patents)


Location History:

  • Moriguchi, JP (1995)
  • Hyogo, JP (1995 - 2007)

Company Filing History:

goldMedal9 out of 27,375 
 
Matsushita Electric Industrial Co., Ltd.
 patents
silverMedal2 out of 655 
 
Matsushita Electronics Corporation
 patents
bronzeMedal1 out of 832,680 
Other
 patents

Years Active: 1995-2007

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12 patents (USPTO):Explore Patents
1. 7308381 - Timing verification method for semiconductor integrated circuit (2007-12-11),
2. 7239997 - Apparatus for statistical LSI delay simulation (2007-07-03),
3. 7222319 - Timing analysis method and apparatus (2007-05-22),
4. 7197728 - Method for setting design margin for LSI (2007-03-27),
5. 6869808 - Method for evaluating property of integrated circuitry (2005-03-22),
6. 6795802 - Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method (2004-09-21),
7. 6278964 - Hot carrier effect simulation for integrated circuits (2001-08-21),
8. 6219630 - Apparatus and method for extracting circuit, system and method for generating information for simulation, and netlist (2001-04-17),
9. 5974247 - Apparatus and method of LSI timing degradation simulation (1999-10-26),
10. 5661413 - Processor utilizing a low voltage data circuit and a high voltage (1997-08-26),
11. 5475825 - Semiconductor device having combined fully associative memories (1995-12-12),
12. 5463751 - Memory device having address translator and comparator for comparing (1995-10-31),
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