Timing verification method for semiconductor integrated circuit

Abstract

Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.